arm-neon-intrinsics.texi

理解和实践操作系统的一本好书

@itemize @bullet
@item uint16x8_t vmlsl_u8 (uint16x8_t, uint8x8_t, uint8x8_t)
@*@emph{Form of expected instruction(s):} @code{vmlsl.u8 @var{q0}, @var{d0}, @var{d0}}
@end itemize


@itemize @bullet
@item int64x2_t vmlsl_s32 (int64x2_t, int32x2_t, int32x2_t)
@*@emph{Form of expected instruction(s):} @code{vmlsl.s32 @var{q0}, @var{d0}, @var{d0}}
@end itemize


@itemize @bullet
@item int32x4_t vmlsl_s16 (int32x4_t, int16x4_t, int16x4_t)
@*@emph{Form of expected instruction(s):} @code{vmlsl.s16 @var{q0}, @var{d0}, @var{d0}}
@end itemize


@itemize @bullet
@item int16x8_t vmlsl_s8 (int16x8_t, int8x8_t, int8x8_t)
@*@emph{Form of expected instruction(s):} @code{vmlsl.s8 @var{q0}, @var{d0}, @var{d0}}
@end itemize


@itemize @bullet
@item int64x2_t vqdmlsl_s32 (int64x2_t, int32x2_t, int32x2_t)
@*@emph{Form of expected instruction(s):} @code{vqdmlsl.s32 @var{q0}, @var{d0}, @var{d0}}
@end itemize


@itemize @bullet
@item int32x4_t vqdmlsl_s16 (int32x4_t, int16x4_t, int16x4_t)
@*@emph{Form of expected instruction(s):} @code{vqdmlsl.s16 @var{q0}, @var{d0}, @var{d0}}
@end itemize




@subsubsection Subtraction

@itemize @bullet
@item uint32x2_t vsub_u32 (uint32x2_t, uint32x2_t)
@*@emph{Form of expected instruction(s):} @code{vsub.i32 @var{d0}, @var{d0}, @var{d0}}
@end itemize


@itemize @bullet
@item uint16x4_t vsub_u16 (uint16x4_t, uint16x4_t)
@*@emph{Form of expected instruction(s):} @code{vsub.i16 @var{d0}, @var{d0}, @var{d0}}
@end itemize


@itemize @bullet
@item uint8x8_t vsub_u8 (uint8x8_t, uint8x8_t)
@*@emph{Form of expected instruction(s):} @code{vsub.i8 @var{d0}, @var{d0}, @var{d0}}
@end itemize


@itemize @bullet
@item int32x2_t vsub_s32 (int32x2_t, int32x2_t)
@*@emph{Form of expected instruction(s):} @code{vsub.i32 @var{d0}, @var{d0}, @var{d0}}
@end itemize


@itemize @bullet
@item int16x4_t vsub_s16 (int16x4_t, int16x4_t)
@*@emph{Form of expected instruction(s):} @code{vsub.i16 @var{d0}, @var{d0}, @var{d0}}
@end itemize


@itemize @bullet
@item int8x8_t vsub_s8 (int8x8_t, int8x8_t)
@*@emph{Form of expected instruction(s):} @code{vsub.i8 @var{d0}, @var{d0}, @var{d0}}
@end itemize


@itemize @bullet
@item uint64x1_t vsub_u64 (uint64x1_t, uint64x1_t)
@*@emph{Form of expected instruction(s):} @code{vsub.i64 @var{d0}, @var{d0}, @var{d0}}
@end itemize


@itemize @bullet
@item int64x1_t vsub_s64 (int64x1_t, int64x1_t)
@*@emph{Form of expected instruction(s):} @code{vsub.i64 @var{d0}, @var{d0}, @var{d0}}
@end itemize


@itemize @bullet
@item float32x2_t vsub_f32 (float32x2_t, float32x2_t)
@*@emph{Form of expected instruction(s):} @code{vsub.f32 @var{d0}, @var{d0}, @var{d0}}
@end itemize


@itemize @bullet
@item uint32x4_t vsubq_u32 (uint32x4_t, uint32x4_t)
@*@emph{Form of expected instruction(s):} @code{vsub.i32 @var{q0}, @var{q0}, @var{q0}}
@end itemize


@itemize @bullet
@item uint16x8_t vsubq_u16 (uint16x8_t, uint16x8_t)
@*@emph{Form of expected instruction(s):} @code{vsub.i16 @var{q0}, @var{q0}, @var{q0}}
@end itemize


@itemize @bullet
@item uint8x16_t vsubq_u8 (uint8x16_t, uint8x16_t)
@*@emph{Form of expected instruction(s):} @code{vsub.i8 @var{q0}, @var{q0}, @var{q0}}
@end itemize


@itemize @bullet
@item int32x4_t vsubq_s32 (int32x4_t, int32x4_t)
@*@emph{Form of expected instruction(s):} @code{vsub.i32 @var{q0}, @var{q0}, @var{q0}}
@end itemize


@itemize @bullet
@item int16x8_t vsubq_s16 (int16x8_t, int16x8_t)
@*@emph{Form of expected instruction(s):} @code{vsub.i16 @var{q0}, @var{q0}, @var{q0}}
@end itemize


@itemize @bullet
@item int8x16_t vsubq_s8 (int8x16_t, int8x16_t)
@*@emph{Form of expected instruction(s):} @code{vsub.i8 @var{q0}, @var{q0}, @var{q0}}
@end itemize


@itemize @bullet
@item uint64x2_t vsubq_u64 (uint64x2_t, uint64x2_t)
@*@emph{Form of expected instruction(s):} @code{vsub.i64 @var{q0}, @var{q0}, @var{q0}}
@end itemize


@itemize @bullet
@item int64x2_t vsubq_s64 (int64x2_t, int64x2_t)
@*@emph{Form of expected instruction(s):} @code{vsub.i64 @var{q0}, @var{q0}, @var{q0}}
@end itemize


@itemize @bullet
@item float32x4_t vsubq_f32 (float32x4_t, float32x4_t)
@*@emph{Form of expected instruction(s):} @code{vsub.f32 @var{q0}, @var{q0}, @var{q0}}
@end itemize


@itemize @bullet
@item uint64x2_t vsubl_u32 (uint32x2_t, uint32x2_t)
@*@emph{Form of expected instruction(s):} @code{vsubl.u32 @var{q0}, @var{d0}, @var{d0}}
@end itemize


@itemize @bullet
@item uint32x4_t vsubl_u16 (uint16x4_t, uint16x4_t)
@*@emph{Form of expected instruction(s):} @code{vsubl.u16 @var{q0}, @var{d0}, @var{d0}}
@end itemize


@itemize @bullet
@item uint16x8_t vsubl_u8 (uint8x8_t, uint8x8_t)
@*@emph{Form of expected instruction(s):} @code{vsubl.u8 @var{q0}, @var{d0}, @var{d0}}
@end itemize


@itemize @bullet
@item int64x2_t vsubl_s32 (int32x2_t, int32x2_t)
@*@emph{Form of expected instruction(s):} @code{vsubl.s32 @var{q0}, @var{d0}, @var{d0}}
@end itemize


@itemize @bullet
@item int32x4_t vsubl_s16 (int16x4_t, int16x4_t)
@*@emph{Form of expected instruction(s):} @code{vsubl.s16 @var{q0}, @var{d0}, @var{d0}}
@end itemize


@itemize @bullet
@item int16x8_t vsubl_s8 (int8x8_t, int8x8_t)
@*@emph{Form of expected instruction(s):} @code{vsubl.s8 @var{q0}, @var{d0}, @var{d0}}
@end itemize


@itemize @bullet
@item uint64x2_t vsubw_u32 (uint64x2_t, uint32x2_t)
@*@emph{Form of expected instruction(s):} @code{vsubw.u32 @var{q0}, @var{q0}, @var{d0}}
@end itemize


@itemize @bullet
@item uint32x4_t vsubw_u16 (uint32x4_t, uint16x4_t)
@*@emph{Form of expected instruction(s):} @code{vsubw.u16 @var{q0}, @var{q0}, @var{d0}}
@end itemize


@itemize @bullet
@item uint16x8_t vsubw_u8 (uint16x8_t, uint8x8_t)
@*@emph{Form of expected instruction(s):} @code{vsubw.u8 @var{q0}, @var{q0}, @var{d0}}
@end itemize


@itemize @bullet
@item int64x2_t vsubw_s32 (int64x2_t, int32x2_t)
@*@emph{Form of expected instruction(s):} @code{vsubw.s32 @var{q0}, @var{q0}, @var{d0}}
@end itemize


@itemize @bullet
@item int32x4_t vsubw_s16 (int32x4_t, int16x4_t)
@*@emph{Form of expected instruction(s):} @code{vsubw.s16 @var{q0}, @var{q0}, @var{d0}}
@end itemize


@itemize @bullet
@item int16x8_t vsubw_s8 (int16x8_t, int8x8_t)
@*@emph{Form of expected instruction(s):} @code{vsubw.s8 @var{q0}, @var{q0}, @var{d0}}
@end itemize


@itemize @bullet
@item uint32x2_t vhsub_u32 (uint32x2_t, uint32x2_t)
@*@emph{Form of expected instruction(s):} @code{vhsub.u32 @var{d0}, @var{d0}, @var{d0}}
@end itemize


@itemize @bullet
@item uint16x4_t vhsub_u16 (uint16x4_t, uint16x4_t)
@*@emph{Form of expected instruction(s):} @code{vhsub.u16 @var{d0}, @var{d0}, @var{d0}}
@end itemize


@itemize @bullet
@item uint8x8_t vhsub_u8 (uint8x8_t, uint8x8_t)
@*@emph{Form of expected instruction(s):} @code{vhsub.u8 @var{d0}, @var{d0}, @var{d0}}
@end itemize


@itemize @bullet
@item int32x2_t vhsub_s32 (int32x2_t, int32x2_t)
@*@emph{Form of expected instruction(s):} @code{vhsub.s32 @var{d0}, @var{d0}, @var{d0}}
@end itemize


@itemize @bullet
@item int16x4_t vhsub_s16 (int16x4_t, int16x4_t)
@*@emph{Form of expected instruction(s):} @code{vhsub.s16 @var{d0}, @var{d0}, @var{d0}}
@end itemize


@itemize @bullet
@item int8x8_t vhsub_s8 (int8x8_t, int8x8_t)
@*@emph{Form of expected instruction(s):} @code{vhsub.s8 @var{d0}, @var{d0}, @var{d0}}
@end itemize


@itemize @bullet
@item uint32x4_t vhsubq_u32 (uint32x4_t, uint32x4_t)
@*@emph{Form of expected instruction(s):} @code{vhsub.u32 @var{q0}, @var{q0}, @var{q0}}
@end itemize


@itemize @bullet
@item uint16x8_t vhsubq_u16 (uint16x8_t, uint16x8_t)
@*@emph{Form of expected instruction(s):} @code{vhsub.u16 @var{q0}, @var{q0}, @var{q0}}
@end itemize


@itemize @bullet
@item uint8x16_t vhsubq_u8 (uint8x16_t, uint8x16_t)
@*@emph{Form of expected instruction(s):} @code{vhsub.u8 @var{q0}, @var{q0}, @var{q0}}
@end itemize


@itemize @bullet
@item int32x4_t vhsubq_s32 (int32x4_t, int32x4_t)
@*@emph{Form of expected instruction(s):} @code{vhsub.s32 @var{q0}, @var{q0}, @var{q0}}
@end itemize


@itemize @bullet
@item int16x8_t vhsubq_s16 (int16x8_t, int16x8_t)
@*@emph{Form of expected instruction(s):} @code{vhsub.s16 @var{q0}, @var{q0}, @var{q0}}
@end itemize


@itemize @bullet
@item int8x16_t vhsubq_s8 (int8x16_t, int8x16_t)
@*@emph{Form of expected instruction(s):} @code{vhsub.s8 @var{q0}, @var{q0}, @var{q0}}
@end itemize


@itemize @bullet
@item uint32x2_t vqsub_u32 (uint32x2_t, uint32x2_t)
@*@emph{Form of expected instruction(s):} @code{vqsub.u32 @var{d0}, @var{d0}, @var{d0}}
@end itemize


@itemize @bullet
@item uint16x4_t vqsub_u16 (uint16x4_t, uint16x4_t)
@*@emph{Form of expected instruction(s):} @code{vqsub.u16 @var{d0}, @var{d0}, @var{d0}}
@end itemize


@itemize @bullet
@item uint8x8_t vqsub_u8 (uint8x8_t, uint8x8_t)
@*@emph{Form of expected instruction(s):} @code{vqsub.u8 @var{d0}, @var{d0}, @var{d0}}
@end itemize


@itemize @bullet
@item int32x2_t vqsub_s32 (int32x2_t, int32x2_t)
@*@emph{Form of expected instruction(s):} @code{vqsub.s32 @var{d0}, @var{d0}, @var{d0}}
@end itemize


@itemize @bullet
@item int16x4_t vqsub_s16 (int16x4_t, int16x4_t)
@*@emph{Form of expected instruction(s):} @code{vqsub.s16 @var{d0}, @var{d0}, @var{d0}}
@end itemize


@itemize @bullet
@item int8x8_t vqsub_s8 (int8x8_t, int8x8_t)
@*@emph{Form of expected instruction(s):} @code{vqsub.s8 @var{d0}, @var{d0}, @var{d0}}
@end itemize


@itemize @bullet
@item uint64x1_t vqsub_u64 (uint64x1_t, uint64x1_t)
@*@emph{Form of expected instruction(s):} @code{vqsub.u64 @var{d0}, @var{d0}, @var{d0}}
@end itemize


@itemize @bullet
@item int64x1_t vqsub_s64 (int64x1_t, int64x1_t)
@*@emph{Form of expected instruction(s):} @code{vqsub.s64 @var{d0}, @var{d0}, @var{d0}}
@end itemize


@itemize @bullet
@item uint32x4_t vqsubq_u32 (uint32x4_t, uint32x4_t)
@*@emph{Form of expected instruction(s):} @code{vqsub.u32 @var{q0}, @var{q0}, @var{q0}}
@end itemize


@itemize @bullet
@item uint16x8_t vqsubq_u16 (uint16x8_t, uint16x8_t)
@*@emph{Form of expected instruction(s):} @code{vqsub.u16 @var{q0}, @var{q0}, @var{q0}}
@end itemize


@itemize @bullet
@item uint8x16_t vqsubq_u8 (uint8x16_t, uint8x16_t)
@*@emph{Form of expected instruction(s):} @code{vqsub.u8 @var{q0}, @var{q0}, @var{q0}}
@end itemize


@itemize @bullet
@item int32x4_t vqsubq_s32 (int32x4_t, int32x4_t)
@*@emph{Form of expected instruction(s):} @code{vqsub.s32 @var{q0}, @var{q0}, @var{q0}}
@end itemize


@itemize @bullet
@item int16x8_t vqsubq_s16 (int16x8_t, int16x8_t)
@*@emph{Form of expected instruction(s):} @code{vqsub.s16 @var{q0}, @var{q0}, @var{q0}}
@end itemize


@itemize @bullet
@item int8x16_t vqsubq_s8 (int8x16_t, int8x16_t)
@*@emph{Form of expected instruction(s):} @code{vqsub.s8 @var{q0}, @var{q0}, @var{q0}}
@end itemize


@itemize @bullet
@item uint64x2_t vqsubq_u64 (uint64x2_t, uint64x2_t)
@*@emph{Form of expected instruction(s):} @code{vqsub.u64 @var{q0}, @var{q0}, @var{q0}}
@end itemize


@itemize @bullet
@item int64x2_t vqsubq_s64 (int64x2_t, int64x2_t)
@*@emph{Form of expected instruction(s):} @code{vqsub.s64 @var{q0}, @var{q0}, @var{q0}}
@end itemize


@itemize @bullet
@item uint32x2_t vsubhn_u64 (uint64x2_t, uint64x2_t)
@*@emph{Form of expected instruction(s):} @code{vsubhn.i64 @var{d0}, @var{q0}, @var{q0}}
@end itemize


@itemize @bullet
@item uint16x4_t vsubhn_u32 (uint32x4_t, uint32x4_t)
@*@emph{Form of expected instruction(s):} @code{vsubhn.i32 @var{d0}, @var{q0}, @var{q0}}
@end itemize


@itemize @bullet
@item uint8x8_t vsubhn_u16 (uint16x8_t, uint16x8_t)
@*@emph{Form of expected instruction(s):} @code{vsubhn.i16 @var{d0}, @var{q0}, @var{q0}}
@end itemize


@itemize @bullet
@item int32x2_t vsubhn_s64 (int64x2_t, int64x2_t)
@*@emph{Form of expected instruction(s):} @code{vsubhn.i64 @var{d0}, @var{q0}, @var{q0}}
@end itemize


@itemize @bullet
@item int16x4_t vsubhn_s32 (int32x4_t, int32x4_t)
@*@emph{Form of expected instruction(s):} @code{vsubhn.i32 @var{d0}, @var{q0}, @var{q0}}
@end itemize


@itemize @bullet
@item int8x8_t vsubhn_s16 (int16x8_t, int16x8_t)
@*@emph{Form of expected instruction(s):} @code{vsubhn.i16 @var{d0}, @var{q0}, @var{q0}}
@end itemize


@itemize @bullet
@item uint32x2_t vrsubhn_u64 (uint64x2_t, uint64x2_t)
@*@emph{Form of expected instruction(s):} @code{vrsubhn.i64 @var{d0}, @var{q0}, @var{q0}}
@end itemize


@itemize @bullet
@item uint16x4_t vrsubhn_u32 (uint32x4_t, uint32x4_t)
@*@emph{Form of expected instruction(s):} @code{vrsubhn.i32 @var{d0}, @var{q0}, @var{q0}}
@end itemize


@itemize @bullet
@item uint8x8_t vrsubhn_u16 (uint16x8_t, uint16x8_t)
@*@emph{Form of expected instruction(s):} @code{vrsubhn.i16 @var{d0}, @var{q0}, @var{q0}}
@end itemize


@itemize @bullet
@item int32x2_t vrsubhn_s64 (int64x2_t, int64x2_t)
@*@emph{Form of expected instruction(s):} @code{vrsubhn.i64 @var{d0}, @var{q0}, @var{q0}}
@end itemize


@itemize @bullet
@item int16x4_t vrsubhn_s32 (int32x4_t, int32x4_t)
@*@emph{Form of expected instruction(s):} @code{vrsubhn.i32 @var{d0}, @var{q0}, @var{q0}}
@end itemize


@itemize @bullet
@item int8x8_t vrsubhn_s16 (int16x8_t, int16x8_t)
@*@emph{Form of expected instruction(s):} @code{vrsubhn.i16 @var{d0}, @var{q0}, @var{q0}}
@end itemize




@subsubsection Comparison (equal-to)

@itemize @bullet
@item uint32x2_t vceq_u32 (uint32x2_t, uint32x2_t)