fxp.h

minix3.1.1源代码

				 */

/* Byte 10 */
#define CCB10_LOOPBACK	0xC0	/* Loopback mode */
#define	    CLB_NORMAL		0x00	/* Normal operation */
#define	    CLB_INTERNAL	0x40	/* Internal loopback */
#define	    CLB_RESERVED	0x80	/* Reserved */
#define	    CLB_EXTERNAL	0xC0	/* External loopback */
#define CCB10_PAL	0x30	/* Pre-amble length */
#define	    CPAL_1		0x00	/* 1 byte */
#define	    CPAL_3		0x10	/* 3 bytes */
#define	    CPAL_7		0x20	/* 7 bytes */
#define	    CPAL_15		0x30	/* 15 bytes */
#define	    CPAL_DEFAULT	CPAL_7
#define CCB10_NSAI		0x08	/* No Source Address Insertion */
#define CCB10_RES1		0x06	/* Reserved, should be set to 1 */
#define CCB10_RES0		0x01	/* Reserved (0) */

/* Byte 11 */
#define CCB11_RES		0xF8	/* Reserved (0) */
#define CCB11_LINPRIO		0x07	/* Linear Priority. 82557 only,
					 * should be zero on other devices.
					 */

/* Byte 12 */
#define CCB12_IS		0xF0	/* Interframe spacing in multiples of
					 * 16 bit times.
					 */
#define	    CIS_DEFAULT			0x60	/* 96 (6 in register) */
#define	CCB12_RES		0x0E	/* Reserved (0) */
#define	CCB12_LPM		0x01	/* Linear Priority Mode. 82557 only,
					 * should be zero on other devices.
					 */

/* Byte 13, 4th byte of IP address for ARP frame filtering. Only valid on
 * 82558 B-step. Should be 0 on other devices.
 */
#define CCB13_DEFAULT		0x00
/* Byte 14, 3rd byte of IP address for ARP fram efiltering. Only valid on
 * 82558 B-step. Should be 0xF2 on other devices.
 */
#define CCB14_DEFAULT		0xF2

/* Byte 15 */
#define CCB15_CRSCDT		0x80	/* CRS or CDT. */
#define CCB15_RES1		0x40	/* Reserved, should be set to one. */
#define CCB15_CRC16		0x20	/* 16-bit CRC. Only on 82559,
					 * should be zero on other devices
					 */
#define CCB15_IUL		0x10	/* Ignore U/L. Reserved on 82557 and
					 * should be set to zero.
					 */
#define CCB15_RES2		0x08	/* Reserved, should be set to one. */
#define CCB15_WAW		0x04	/* Wait After Win. Reserved on 82557,
					 * should be set to zero.
					 */
#define CCB15_BD		0x02	/* Broadcast disable */
#define CCB15_PM		0x01	/* Promiscuous mode */

/* Byte 16. FC Delay Least Significant Byte. Reserved on the 82557 and
 * should be set to zero.
 */
#define CCB16_DEFAULT		0x00

/* Byte 17. FC Delay Most Significant Byte. This byte is reserved on the
 * 82557 and should be set to 0x40.
 */
#define CCB17_DEFAULT		0x40

/* Byte 18 */
#define CCB18_RES1		0x80	/* Reserved, should be set to 1 */
#define CCB18_PFCT		0x70	/* Priority Flow Control Threshold.
					 * Reserved on the 82557 and should
					 * be set to 1. All bits 1 (disabled)
					 * is the recommended default.
					 */
#define CCB18_LROK		0x08	/* Long Receive OK. Reserved on the
					 * 82557 and should be set to zero.
					 * Required for VLANs.
					 */
#define CCB18_RCRCT		0x04	/* Receive CRC Transfer */
#define CCB18_PE		0x02	/* Padding Enable */
#define CCB18_SE		0x01	/* Stripping Enable */

/* Byte 19 */
#define CCB19_FDPE		0x80	/* Full Duplex Pin Enable */
#define CCB19_FFD		0x40	/* Force Full Duplex */
#define CCB19_RFC		0x20	/* Reject FC. Reserved on the 82557
					 * and should be set to zero.
					 */
#define CCB19_FDRSTAFC		0x10	/* Full Duplex Restart Flow Control.
					 * Reserved on the 82557 and should be
					 * set to zero.
					 */
#define CCB19_FDRSTOFC		0x08	/* Full Duplex Restop Flow Control.
					 * Reserved on the 82557 and should be
					 * set to zero.
					 */
#define CCB19_FDTFCD		0x04	/* Full Duplex Transmit Flow Control
					 * Disable. Reserved on the 82557 and
					 * should be set to zero.
					 */
#define CCB19_MPWD		0x02	/* Magic Packet Wake-up Disable.
					 * Reserved on the 82557 and 82559ER
					 * and should be set to zero.
					 */
#define CCB19_AW		0x01	/* Address Wake-up (82558 A-step) and
					 * IA Match Wake Enable (82558 B-step)
					 * Reserved on the 82557 and 82559 and
					 * should be set to zero.
					 */

/* Byte 20 */
#define CCB20_RES		0x80	/* Reserved (0) */
#define CCB20_MIA		0x40	/* Multiple IA */
#define CCB20_PFCL		0x20	/* Priority FC Location. Reserved on
					 * the 82557 and should be set to 1.
					 */
#define CCB20_RES1		0x1F	/* Reserved, should be set to 1 */

/* Byte 21 */
#define CCB21_RES		0xF0	/* Reserved (0) */
#define CCB21_MA		0x08	/* Multicast All */
#define CCB21_RES1_MASK		0x07	/* Reserved, should be set to 5 */
#define     CCB21_RES21			0x05

/* Transmit (4) */
struct tx
{
	u16_t tx_status;
	u16_t tx_command;
	u32_t tx_linkaddr;
	u32_t tx_tbda;
	u16_t tx_size;
	u8_t tx_tthresh;
	u8_t tx_ntbd;
	u8_t tx_buf[ETH_MAX_PACK_SIZE_TAGGED];
};

#define TXS_C		0x8000	/* Transmit DMA has completed */
#define TXS_RES		0x4000	/* Reserved */
#define TXS_OK		0x2000	/* Command was executed without error */
#define TXS_U		0x1000	/* This or previous frame encoutered underrun */
#define TXS_RES1	0x0FFF	/* Reserved (0) */

#define TXC_EL		0x8000	/* End of List */
#define TXC_S		0x4000	/* Suspend after this CB */
#define TXC_I		0x2000	/* Interrupt after this CB */
#define TXC_CID_MASK	0x1F00	/* CNA Interrupt Delay */
#define TXC_RES		0x00E0	/* Reserved (0) */
#define TXC_NC		0x0010	/* No CRC and Source Address Insertion */
#define TXC_SF		0x0008	/* Not in Simplified Mode */
#define TXC_CMD		0x0007	/* Command */

#define TXSZ_EOF	0x8000	/* End of Frame */
#define TXSZ_RES	0x4000	/* Reserved (0) */
#define TXSZ_COUNT	0x3FFF	/* Transmit Byte Count */

#define TX_TBDA_NIL	0xFFFFFFFF	/* Null Pointer for TBD Array */

#define TXTT_MIN	0x01	/* Minimum for Transmit Threshold */
#define TXTT_MAX	0xE0	/* Maximum for Transmit Threshold */

/* Statistical Counters */
struct sc
{
	u32_t sc_tx_good;	/* Transmit Good Frames */
	u32_t sc_tx_maxcol;	/* Transmit Maximum Collisions errors */
	u32_t sc_tx_latecol;	/* Transmit Late Collisions errors */
	u32_t sc_tx_underrun;	/* Transmit Underrun errors */
	u32_t sc_tx_crs;	/* Transmit Lost Carrier Sense */
	u32_t sc_tx_defered;	/* Transmit Defered */
	u32_t sc_tx_scol;	/* Transmit Single Collision */
	u32_t sc_tx_mcol;	/* Transmit Multiple Collisions */
	u32_t sc_tx_totcol;	/* Transmit Total Collisions */
	u32_t sc_rx_good;	/* Receive Good Frames */
	u32_t sc_rx_crc;	/* Receive CRC errors */
	u32_t sc_rx_align;	/* Receive Alignment errors */
	u32_t sc_rx_resource;	/* Receive Resource errors */
	u32_t sc_rx_overrun;	/* Receive Overrun errors */
	u32_t sc_rx_cd;		/* Receive Collision Detect errors */
	u32_t sc_rx_short;	/* Receive Short Frame errors */

				/* Short form ends here. The magic number will
				 * be stored in the next field.
				 */

	u32_t sc_tx_fcp;	/* Transmit Flow Control Pause */
	u32_t sc_rx_fcp;	/* Receive Flow Control Pause */
	u32_t sc_rx_fcu;	/* Receive Flow Control Unsupported */

				/* Longer form (82558 and later) ends here.
				 * The magic number will be stored in the
				 * next field.
				 */

	u32_t sc_tx_tco;	/* Transmit TCO frames */
	u32_t sc_rx_tco;	/* Receive TCO frames */
	u32_t sc_magic;		/* Dump of counters completed */
};

#define SCM_DSC		0x0000A005	/* Magic for SC_CU_DUMP_SC command */
#define SCM_DRSC	0x0000A007	/* Magic for SC_CU_DUMP_RSET_SC cmd */

/* Receive Frame Descriptor (RFD) */
struct rfd
{
	u16_t rfd_status;
	u16_t rfd_command;
	u32_t rfd_linkaddr;
	u32_t rfd_reserved;
	u16_t rfd_res;
	u16_t rfd_size;
	u8_t rfd_buf[ETH_MAX_PACK_SIZE_TAGGED];
};

#define RFDS_C		0x8000	/* Frame Reception Completed */
#define RFDS_RES	0x4000	/* Reserved (0) */
#define RFDS_OK		0x2000	/* Frame received without any errors */
#define RFDS_RES1	0x1000	/* Reserved */
#define RFDS_CRCERR	0x0800	/* CRC error */
#define RFDS_ALIGNERR	0x0400	/* Alignment error */
#define RFDS_OUTOFBUF	0x0200	/* Ran out of buffer space (frame is frager
				 * than supplied buffer).
				 */
#define RFDS_DMAOVR	0x0100	/* DMA overrun failure */
#define RFDS_TOOSHORT	0x0080	/* Frame Too Short */
#define RFDS_RES2	0x0040	/* Reserved */
#define RFDS_TYPED	0x0020	/* Frame Is Typed (Type/Length field is 0 or
				 * >1500)
				 */
#define RFDS_RXERR	0x0010	/* Receive Error */
#define RFDS_RES3	0x0008	/* Reserved */
#define RFDS_NOAM	0x0004	/* No Address Match */
#define RFDS_NOAIAM	0x0002	/* No IA Address Match */
#define RFDS_RXCOL	0x0001	/* Collition Detected During Reception (82557
				 * and 82558 only)
				 */
#define RFDS_TCO	0x0001	/* TCO Packet (82559 and later) */

#define RFDC_EL		0x8000	/* End of List */
#define RFDC_S		0x4000	/* Suspend */
#define RFDC_RES	0x3FE0	/* Reserved (0) */
#define RFDC_H		0x0010	/* Header RFD */
#define RFDC_SF		0x0008	/* (Not) Simplified Mode */
#define RFDC_RES1	0x0007	/* Reserved (0) */

#define RFDR_EOF	0x8000	/* End of Frame (all data is in the buffer) */
#define RFDR_F		0x4000	/* Finished updating the count field */
#define RFDR_COUNT	0x3FFF	/* Actual Count */

#define RFDSZ_RES	0xC000	/* Reserved (0) */
#define RFDSZ_SIZE	0x3FFF	/* Buffer Size */

/* EEPROM commands */
#define EEPROM_READ_PREFIX	0x6	/* Read command */
#define EEPROM_PREFIX_LEN	3	/* Start bit and two command bits */

/* EEPROM timing parameters */
#define EECS_DELAY	1	/* Keep EECS low for at least EECS_DELAY
				 * microseconds
				 */
#define EESK_PERIOD	4	/* A cycle of driving EESK high followed by
				 * driving EESK low should take at least
				 * EESK_PERIOD microseconds
				 */

/* Special registers in the 82555 (and compatible) PHYs. Should be moved
 * to a separate file if other drivers need this too.
 */
#define MII_SCR		0x10	/* Status and Control Register */
#define	    MII_SCR_FC		0x8000	/* Flow Control */
#define	    MII_SCR_T4E		0x4000	/* Enable T4 unless auto-negotiation */
#define	    MII_SCR_CRSDC	0x2000	/* RX100 CRS Disconnect */
#define	    MII_SCR_RES		0x1000	/* Reserved */
#define	    MII_SCR_RCVSYNC	0x0800	/* RCV De-Serializer in sync */
#define	    MII_SCR_100DOWN	0x0400	/* 100Base-T Power Down */
#define	    MII_SCR_10DOWN	0x0200	/* 10Base-T Power Down */
#define	    MII_SCR_POLARITY	0x0100	/* 10Base-T Polarity */
#define	    MII_SCR_RES_1	0x00F8	/* Reserved */
#define	    MII_SCR_T4		0x0004	/* 100Base-T4 negotiated */
#define	    MII_SCR_100		0x0002	/* 100 Mbps negotiated */
#define	    MII_SCR_FD		0x0001	/* Full Duplex negotiated */

/*
 * $PchId: fxp.h,v 1.1 2004/11/23 14:34:03 philip Exp $
 */