cstartup_sam7.lst

一个AT91SAM7X256 USART驱动实验

     62                (AT91C_CKGR_MUL & (72 << 16)) | (AT91C_CKGR_DIV & 14);
   \   0000001A   1949               LDR      R1,??AT91F_LowLevelInit_0+0xC  ;; 0xfffffc2c
   \   0000001C   194A               LDR      R2,??AT91F_LowLevelInit_0+0x10  ;; 0x10483f0e
   \   0000001E   0A60               STR      R2,[R1, #+0]
   \   00000020   0422               MOVS     R2,#+4
   \   00000022   0423               MOVS     R3,#+4
     63              // Wait for PLL stabilization
     64              while( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCK) );
   \                     ??AT91F_LowLevelInit_2:
   \   00000024   0168               LDR      R1,[R0, #+0]
   \   00000026   1942               TST      R1,R3
   \   00000028   FCD0               BEQ      ??AT91F_LowLevelInit_2
     65              // Wait until the master clock is established for the case we already turn on the PLL
     66              while( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) );
   \                     ??AT91F_LowLevelInit_3:
   \   0000002A   0821               MOVS     R1,#+8
   \   0000002C   0368               LDR      R3,[R0, #+0]
   \   0000002E   0B42               TST      R3,R1
   \   00000030   FBD0               BEQ      ??AT91F_LowLevelInit_3
     67          
     68              /////////////////////////////////////////////////////////////////////////////////////////////////////
     69              // Init PMC Step 3.
     70              // Selection of Master Clock MCK (equal to Processor Clock PCK) equal to PLL/2 = 48MHz
     71              // The PMC_MCKR register must not be programmed in a single write operation (see. Product Errata Sheet)
     72              /////////////////////////////////////////////////////////////////////////////////////////////////////
     73              AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_PRES_CLK_2;
   \   00000032   154B               LDR      R3,??AT91F_LowLevelInit_0+0x14  ;; 0xfffffc30
   \   00000034   1A60               STR      R2,[R3, #+0]
     74              // Wait until the master clock is established
     75              while( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) );
   \                     ??AT91F_LowLevelInit_4:
   \   00000036   0268               LDR      R2,[R0, #+0]
   \   00000038   0A42               TST      R2,R1
   \   0000003A   FCD0               BEQ      ??AT91F_LowLevelInit_4
     76          
     77              AT91C_BASE_PMC->PMC_MCKR |= AT91C_PMC_CSS_PLL_CLK;
   \   0000003C   1A68               LDR      R2,[R3, #+0]
   \   0000003E   0324               MOVS     R4,#+3
   \   00000040   1443               ORRS     R4,R4,R2
   \   00000042   1C60               STR      R4,[R3, #+0]
     78              // Wait until the master clock is established
     79              while( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) );
   \                     ??AT91F_LowLevelInit_5:
   \   00000044   0268               LDR      R2,[R0, #+0]
   \   00000046   0A42               TST      R2,R1
   \   00000048   FCD0               BEQ      ??AT91F_LowLevelInit_5
     80          
     81              /////////////////////////////////////////////////////////////////////////////////////////////////////
     82              //  Disable Watchdog (write once register)
     83              /////////////////////////////////////////////////////////////////////////////////////////////////////
     84              AT91C_BASE_WDTC->WDTC_WDMR = AT91C_WDTC_WDDIS;
   \   0000004A   1048               LDR      R0,??AT91F_LowLevelInit_0+0x18  ;; 0xfffffd44
   \   0000004C   0903               LSLS     R1,R1,#+12
   \   0000004E   0160               STR      R1,[R0, #+0]
     85          
     86              /////////////////////////////////////////////////////////////////////////////////////////////////////
     87              // Set up the default interrupts handler vectors
     88              /////////////////////////////////////////////////////////////////////////////////////////////////////
     89              AT91C_BASE_AIC->AIC_SVR[0] = (int) AT91F_Default_FIQ_handler ;
   \   00000050   0F48               LDR      R0,??AT91F_LowLevelInit_0+0x1C  ;; 0xfffff080
   \   00000052   1049               LDR      R1,??AT91F_LowLevelInit_0+0x20  ;; AT91F_Default_FIQ_handler
   \   00000054   0160               STR      R1,[R0, #+0]
     90              for (i=1;i < 31; i++)
   \   00000056   0120               MOVS     R0,#+1
   \   00000058   0D4A               LDR      R2,??AT91F_LowLevelInit_0+0x1C  ;; 0xfffff080
   \   0000005A   0F4B               LDR      R3,??AT91F_LowLevelInit_0+0x24  ;; AT91F_Default_IRQ_handler
     91              {
     92                  AT91C_BASE_AIC->AIC_SVR[i] = (int) AT91F_Default_IRQ_handler ;
   \                     ??AT91F_LowLevelInit_6:
   \   0000005C   8100               LSLS     R1,R0,#+2
   \   0000005E   5350               STR      R3,[R2, R1]
     93              }
   \   00000060   401C               ADDS     R0,R0,#+1
   \   00000062   1F28               CMP      R0,#+31
   \   00000064   FADB               BLT      ??AT91F_LowLevelInit_6
     94              AT91C_BASE_AIC->AIC_SPU  = (int) AT91F_Spurious_handler ;
   \   00000066   0D48               LDR      R0,??AT91F_LowLevelInit_0+0x28  ;; 0xfffff134
   \   00000068   0D49               LDR      R1,??AT91F_LowLevelInit_0+0x2C  ;; AT91F_Spurious_handler
   \   0000006A   0160               STR      R1,[R0, #+0]
     95          }
   \   0000006C   10BC               POP      {R4}
   \   0000006E   01BC               POP      {R0}
   \   00000070   0047               BX       R0               ;; return
   \   00000072   C046               Nop      
   \                     ??AT91F_LowLevelInit_0:
   \   00000074   20FCFFFF           DC32     0xfffffc20
   \   00000078   01400000           DC32     0x4001
   \   0000007C   68FCFFFF           DC32     0xfffffc68
   \   00000080   2CFCFFFF           DC32     0xfffffc2c
   \   00000084   0E3F4810           DC32     0x10483f0e
   \   00000088   30FCFFFF           DC32     0xfffffc30
   \   0000008C   44FDFFFF           DC32     0xfffffd44
   \   00000090   80F0FFFF           DC32     0xfffff080
   \   00000094   ........           DC32     AT91F_Default_FIQ_handler
   \   00000098   ........           DC32     AT91F_Default_IRQ_handler
   \   0000009C   34F1FFFF           DC32     0xfffff134
   \   000000A0   ........           DC32     AT91F_Spurious_handler

   Maximum stack usage in bytes:

     Function           CSTACK
     --------           ------
     AT91F_LowLevelInit     8


   Segment part sizes:

     Function/Label     Bytes
     --------------     -----
     AT91F_LowLevelInit  164
      Others               8

 
 172 bytes in segment CODE
 
 164 bytes of CODE memory (+ 8 bytes shared)

Errors: none
Warnings: none