cstartup.s79

一个AT91SAM7X256 CAN计数器中断实验

;------------------------------------------------------------------------------
;-          ATMEL Microcontroller Software Support  -  ROUSSET  -
;------------------------------------------------------------------------------
;- DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
;- IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
;- MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
;- DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
;- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
;- LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
;- OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
;- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
;- NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
;- EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;-------------------------------------------------------------------------------
;-
;- Copyright ART Ltd 2006. All rights reserved.
;-
;- File: Cstartup.s79
;-
;- Data: 06.06.26
;-
;-------------------------------------------------------------------------------
#include "config.inc"

;---------------------------------------------------------------
; ?RESET
; Reset Vector.
; Normally, segment INTVEC is linked at address 0.
; For debugging purposes, INTVEC may be placed at other
; addresses.
; A debugger that honors the entry point will start the
; program in a normal way even if INTVEC is not at address 0.
;-------------------------------------------------------------
        PROGRAM ?RESET
        RSEG    INTRAMEND_REMAP

        RSEG    ICODE:CODE:ROOT(2)
        CODE32  ; Always ARM mode after reset	
        ORG     0
reset		

;-------------------------------------------------------------------------------
;- Exception vectors
;-------------------------------------------------------------------------------
;- These vectors can be read at address 0 or at RAM address
;- They ABSOLUTELY requires to be in relative addresssing mode in order to
;- guarantee a valid jump. For the moment, all are just looping.
;- If an exception occurs before remap, this would result in an infinite loop.
;- To ensure if a exeption occurs before start application to infinite loop.
;-------------------------------------------------------------------------------
start:
                B       InitReset
undefvec:
                B       undefvec
swivec:
                B       swivec
pabtvec:
                B       pabtvec
dabtvec:
                B       dabtvec
rsvdvec:
                B       rsvdvec
irqvec:
                B       irq
fiqvec:
                B       fiq

;------------------------------------------------------------------------------
;- Manage exception     : The exception must be ensure in ARM mode
;- Treatments           : FIQ Controller Interrupt Handler.
;- Called Functions     : AIC_FVR[interrupt]
;------------------------------------------------------------------------------
fiq:
;- Save and r0 in FIQ_Register
       mov      r9, r0
	   ldr      r0, [r8, #AIC_FVR]
       msr      CPSR_c, #0xd3

;- Save scratch/used registers and LR in User Stack
       stmfd    sp!, {r1-r3, r12, lr}

;- Branch to the routine pointed by the AIC_FVR
       mov      r14, pc
       bx       r0

;- Restore scratch/used registers and LR from User Stack
       ldmia    sp!, {r1-r3, r12, lr}

;- Leave Interrupts disabled and switch back in FIQ mode
       msr      CPSR_c, #0xd1

;- Restore the R0 ARM_MODE_SVC register
       mov      r0, r9

;- Restore the Program Counter using the LR_fiq directly in the PC
       subs     pc, lr, #4

;------------------------------------------------------------------------------
;- Manage exception     : The exception must be ensure in ARM mode
;- Treatments           : IRQ Controller Interrupt Handler.
;- Called Functions     : AIC_IVR[interrupt]
;------------------------------------------------------------------------------
irq:

;-------------------------
;- Manage Exception Entry
;-------------------------
;- Adjust and save LR_irq in IRQ stack
       sub      lr, lr, #4
       stmfd    sp!, {lr}

;- Save r0 and SPSR (need to be saved for nested interrupt)
       mrs      r14, SPSR
       stmfd    sp!, {r0, r14}

;- Write in the IVR to support Protect Mode
       ldr      r14, =AT91C_BASE_AIC
       ldr      r0 , [r14, #AIC_IVR]
       str      r14, [r14, #AIC_IVR]

;- Enable Interrupt and Switch in Supervisor Mode
       msr      CPSR_c, #0x13

;- Save scratch/used registers and LR in User Stack
       stmfd    sp!, {r1-r3, r12, r14}

;----------------------------------------------
;- Branch to the routine pointed by the AIC_IVR
;----------------------------------------------
       mov      r14, pc
       bx       r0

;----------------------------------------------
;- Manage Exception Exit
;----------------------------------------------
;- Restore scratch/used registers and LR from User Stack
       ldmia    sp!, {r1-r3, r12, r14}

;- Disable Interrupt and switch back in IRQ mode
       msr      CPSR_c, #0x92

;- Mark the End of Interrupt on the AIC
       ldr      r14, =AT91C_BASE_AIC
       str      r14, [r14, #AIC_EOICR]

;- Restore SPSR_irq and r0 from IRQ stack
       ldmia    sp!, {r0, r14}
       msr      SPSR_cxsf, r14

;- Restore adjusted  LR_irq from IRQ stack directly in the PC
       ldmia    sp!, {pc}^

;------------------------------------------------------------------------------
;- Low level Init is performed in a C function: AT91F_LowLevelInit
;- Init Stack Pointer to a valid memory area before calling AT91F_LowLevelInit
;------------------------------------------------------------------------------
;- Retrieve end of RAM address
;__iramend  EQU INTRAMEND_REMAP              ;- Segment begin
__iramend   EQU SFB(INTRAMEND_REMAP)         ;- Segment begin
       EXTERN   AT91F_LowLevelInit
InitReset:
       ldr      r13, =__iramend              ;- Temporary stack
       ldr      r0, =AT91F_LowLevelInit
       mov      lr, pc
       bx       r0

;------------------------------------------------------------------------------
;- Top of Stack Definition
;------------------------------------------------------------------------------
;- Interrupt and Supervisor Stack are located at the top of internal memory in
;- order to speed the exception handling context saving and restoring.
;- ARM_MODE_SVC (App, C) Stack is located at the top of the external memory.
;------------------------------------------------------------------------------
;- 3 words to be saved per interrupt priority level
IRQ_STACK_SIZE          EQU     (3*8*4)

;------------------------------------------------------------------------------
;- Setup the stack for each mode
;------------------------------------------------------------------------------
        ldr     r0, =__iramend

;- Set up Fast Interrupt Mode and set FIQ Mode Stack
        msr     CPSR_c, #0xd1
;- Init the FIQ register
        ldr     r8, =AT91C_BASE_AIC

;- Set up Interrupt Mode and set IRQ Mode Stack
        msr     CPSR_c, #0xd2
        mov     r13, r0
        sub     r0, r0, #IRQ_STACK_SIZE

;- Enable interrupt & Set Supervisor Mode Stack
        msr     CPSR_c, #0x13
        mov     r13, r0

;---------------------------------------------------------------
; ?CSTARTUP
;---------------------------------------------------------------
        EXTERN  __segment_init
; Initialize segments.
        ldr     r0, =__segment_init
        mov     lr, pc
		bx      r0

        EXTERN  main
        PUBLIC  __main
?jump_to_main:
        ldr     lr, =?call_exit
        ldr     r0, =main
__main:
        bx      r0

;------------------------------------------------------------------------------
;- Loop for ever
;---------------
;- End of application. Normally, never occur.
;------------------------------------------------------------------------------
?call_exit:
End
        b       End

;------------------------------------------------------------------------------
;- Exception Vectors
;------------------------------------------------------------------------------
        CODE32  ; Always ARM mode after exeption
        PUBLIC  AT91F_Default_FIQ_handler
        PUBLIC  AT91F_Default_IRQ_handler
        PUBLIC  AT91F_Spurious_handler

AT91F_Default_FIQ_handler:
        b       AT91F_Default_FIQ_handler

AT91F_Default_IRQ_handler:
        b       AT91F_Default_IRQ_handler

AT91F_Spurious_handler:
        b       AT91F_Spurious_handler

;------------------------------------------------------------------------------
        PUBLIC  ARMDisableInt
ARMDisableInt:
        STMFD   sp!, {r0}
        MRS     r0, CPSR
        ORR     r0, r0, #0x80
        MSR     CPSR_cxsf, r0
        LDMFD   sp!, {r0}
        MOV     pc, lr

        PUBLIC  ARMEnableInt
ARMEnableInt:
        STMFD   sp!, {r0}
        MRS     r0, CPSR
        BIC     r0, r0, #0x80
        MSR     CPSR_cxsf, r0
        LDMFD   sp!, {r0}
        MOV     pc, lr

;------------------------------------------------------------------------------
            END