📄 cstartup.lst
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###############################################################################
# #
# IAR Systems ARM Assembler V4.40A/W32 15/Jun/2007 10:46:46 #
# Copyright 1999-2006 IAR Systems. All rights reserved. #
# #
# Source file = E:\课题\分布式电磁频谱侦察监视系统\ARM学习资料\实例\IAR实验代码\实验三\AT91SAM7X256定时器实验\SrcIAR\Cstartup.s79#
# List file = E:\课题\分布式电磁频谱侦察监视系统\ARM学习资料\实例\IAR实验代码\实验三\AT91SAM7X256定时器实验\FLASH_FLASH\List\Cstartup.lst#
# Object file = E:\课题\分布式电磁频谱侦察监视系统\ARM学习资料\实例\IAR实验代码\实验三\AT91SAM7X256定时器实验\FLASH_FLASH\Obj\Cstartup.r79#
# Command line = E:\课题\分布式电磁频谱侦察监视系统\ARM学习资料\实例\IAR实验代码\实验三\AT91SAM7X256定时器实验\SrcIAR\Cstartup.s79 #
# -OE:\课题\分布式电磁频谱侦察监视系统\ARM学习资料\实例\IAR实验代码\实验三\AT91SAM7X256定时器实验\FLASH_FLASH\Obj\ #
# -s+ -M<> -w+ -r #
# -LE:\课题\分布式电磁频谱侦察监视系统\ARM学习资料\实例\IAR实验代码\实验三\AT91SAM7X256定时器实验\FLASH_FLASH\List\ #
# -t8 --cpu ARM7TDMI --fpu None #
# -IC:\Program Files\IAR Systems\Embedded Workbench 4.0 Evaluation\ARM\INC\ #
# -IE:\课题\分布式电磁频谱侦察监视系统\ARM学习资料\实例\IAR实验代码\实验三\AT91SAM7X256定时器实验\..\..\ #
# #
###############################################################################
1 00000000 ;-----------------------------------------------
-------------------------------
2 00000000 ;- ATMEL Microcontroller Software
Support - ROUSSET -
3 00000000 ;-----------------------------------------------
-------------------------------
4 00000000 ;- DISCLAIMER: THIS SOFTWARE IS PROVIDED BY
ATMEL "AS IS" AND ANY EXPRESS OR
5 00000000 ;- IMPLIED WARRANTIES, INCLUDING, BUT NOT
LIMITED TO, THE IMPLIED WARRANTIES OF
6 00000000 ;- MERCHANTABILITY, FITNESS FOR A PARTICULAR
PURPOSE AND NON-INFRINGEMENT ARE
7 00000000 ;- DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE
FOR ANY DIRECT, INDIRECT,
8 00000000 ;- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENT
IAL DAMAGES (INCLUDING, BUT NOT
9 00000000 ;- LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
OR SERVICES; LOSS OF USE, DATA,
10 00000000 ;- OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF
11 00000000 ;- LIABILITY, WHETHER IN CONTRACT, STRICT
LIABILITY, OR TORT (INCLUDING
12 00000000 ;- NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
OUT OF THE USE OF THIS SOFTWARE,
13 00000000 ;- EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
DAMAGE.
14 00000000 ;-----------------------------------------------
--------------------------------
15 00000000 ;-
16 00000000 ;- Copyright ART Ltd 2006. All rights reserved.
17 00000000 ;-
18 00000000 ;- File: Cstartup.s79
19 00000000 ;-
20 00000000 ;- Data: 06.06.26
21 00000000 ;-
22 00000000 ;-----------------------------------------------
--------------------------------
23 00000000 #include "config.inc"
24 00000000
25 00000000 ;-----------------------------------------------
----------------
26 00000000 ; ?RESET
27 00000000 ; Reset Vector.
28 00000000 ; Normally, segment INTVEC is linked at address
0.
29 00000000 ; For debugging purposes, INTVEC may be placed
at other
30 00000000 ; addresses.
31 00000000 ; A debugger that honors the entry point will
start the
32 00000000 ; program in a normal way even if INTVEC is not
at address 0.
33 00000000 ;-----------------------------------------------
--------------
34 00000000 PROGRAM ?RESET
35 00000000 RSEG INTRAMEND_REMAP
36 00000000
37 00000000 RSEG ICODE:CODE:ROOT(2)
38 00000000 CODE32 ; Always ARM mode after reset
39 00000000 ORG 0
40 00000000 reset
41 00000000
42 00000000 ;-----------------------------------------------
--------------------------------
43 00000000 ;- Exception vectors
44 00000000 ;-----------------------------------------------
--------------------------------
45 00000000 ;- These vectors can be read at address 0 or at
RAM address
46 00000000 ;- They ABSOLUTELY requires to be in relative
addresssing mode in order to
47 00000000 ;- guarantee a valid jump. For the moment, all
are just looping.
48 00000000 ;- If an exception occurs before remap, this
would result in an infinite loop.
49 00000000 ;- To ensure if a exeption occurs before start
application to infinite loop.
50 00000000 ;-----------------------------------------------
--------------------------------
51 00000000 start:
52 00000000 220000EA B InitReset
53 00000004 undefvec:
54 00000004 FEFFFFEA B undefvec
55 00000008 swivec:
56 00000008 FEFFFFEA B swivec
57 0000000C pabtvec:
58 0000000C FEFFFFEA B pabtvec
59 00000010 dabtvec:
60 00000010 FEFFFFEA B dabtvec
61 00000014 rsvdvec:
62 00000014 FEFFFFEA B rsvdvec
63 00000018 irqvec:
64 00000018 0A0000EA B irq
65 0000001C fiqvec:
66 0000001C FFFFFFEA B fiq
67 00000020
68 00000020 ;-----------------------------------------------
-------------------------------
69 00000020 ;- Manage exception : The exception must be
ensure in ARM mode
70 00000020 ;- Treatments : FIQ Controller
Interrupt Handler.
71 00000020 ;- Called Functions : AIC_FVR[interrupt]
72 00000020 ;-----------------------------------------------
-------------------------------
73 00000020 fiq:
74 00000020 ;- Save and r0 in FIQ_Register
75 00000020 0090A0E1 mov r9, r0
76 00000024 040198E5 ldr r0, [r8, #AIC_FVR]
77 00000028 D3F021E3 msr CPSR_c, #0xd3
78 0000002C
79 0000002C ;- Save scratch/used registers and LR in User
Stack
80 0000002C 0E502DE9 stmfd sp!, {r1-r3, r12, lr}
81 00000030
82 00000030 ;- Branch to the routine pointed by the
AIC_FVR
83 00000030 0FE0A0E1 mov r14, pc
84 00000034 10FF2FE1 bx r0
85 00000038
86 00000038 ;- Restore scratch/used registers and LR from
User Stack
87 00000038 0E50BDE8 ldmia sp!, {r1-r3, r12, lr}
88 0000003C
89 0000003C ;- Leave Interrupts disabled and switch back in
FIQ mode
90 0000003C D1F021E3 msr CPSR_c, #0xd1
91 00000040
92 00000040 ;- Restore the R0 ARM_MODE_SVC register
93 00000040 0900A0E1 mov r0, r9
94 00000044
95 00000044 ;- Restore the Program Counter using the LR_fiq
directly in the PC
96 00000044 04F05EE2 subs pc, lr, #4
97 00000048
98 00000048 ;-----------------------------------------------
-------------------------------
99 00000048 ;- Manage exception : The exception must be
ensure in ARM mode
100 00000048 ;- Treatments : IRQ Controller
Interrupt Handler.
101 00000048 ;- Called Functions : AIC_IVR[interrupt]
102 00000048 ;-----------------------------------------------
-------------------------------
103 00000048 irq:
104 00000048
105 00000048 ;-------------------------
106 00000048 ;- Manage Exception Entry
107 00000048 ;-------------------------
108 00000048 ;- Adjust and save LR_irq in IRQ stack
109 00000048 04E04EE2 sub lr, lr, #4
110 0000004C 00402DE9 stmfd sp!, {lr}
111 00000050
112 00000050 ;- Save r0 and SPSR (need to be saved for nested
interrupt)
113 00000050 00E04FE1 mrs r14, SPSR
114 00000054 01402DE9 stmfd sp!, {r0, r14}
115 00000058
116 00000058 ;- Write in the IVR to support Protect
Mode
117 00000058 B8E09FE5 ldr r14, =AT91C_BASE_AIC
118 0000005C 00019EE5 ldr r0 , [r14, #AIC_IVR]
119 00000060 00E18EE5 str r14, [r14, #AIC_IVR]
120 00000064
121 00000064 ;- Enable Interrupt and Switch in Supervisor
Mode
122 00000064 13F021E3 msr CPSR_c, #0x13
123 00000068
124 00000068 ;- Save scratch/used registers and LR in User
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