📄 cstartup.lst
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138 00000054
139 00000011 ARM_MODE_FIQ EQU 0x11
140 00000012 ARM_MODE_IRQ EQU 0x12
141 00000013 ARM_MODE_SVC EQU 0x13
142 00000054
143 00000080 I_BIT EQU 0x80
144 00000040 F_BIT EQU 0x40
145 00000054
146 00000054 ;-----------------------------------------------
-------------------------------
147 00000054 ;- Setup the stack for each mode
148 00000054 ;-------------------------------
149 00000054 84009FE5 ldr r0, =__iramend
150 00000058
151 00000058 ;- Set up Fast Interrupt Mode and set FIQ Mode
Stack
152 00000058 D1F021E3 msr CPSR_c, #ARM_MODE_FIQ |
I_BIT |
F_BIT
153 0000005C ;- Init the FIQ register
154 0000005C 84809FE5 ldr r8, =AT91C_BASE_AIC
155 00000060
156 00000060 ;- Set up Interrupt Mode and set IRQ Mode
Stack
157 00000060 D2F021E3 msr CPSR_c, #ARM_MODE_IRQ |
I_BIT |
F_BIT
158 00000064 00D0A0E1 mov r13, r0
; Init stack
IRQ
159 00000068 400040E2 sub r0, r0, #IRQ_STACK_SIZE
160 0000006C
161 0000006C ;- Enable interrupt & Set up Supervisor Mode and
set Supervisor Mode Stack
162 0000006C 13F021E3 msr CPSR_c, #ARM_MODE_SVC
163 00000070 00D0A0E1 mov r13, r0
164 00000074
165 00000074
166 00000074 ;-----------------------------------------------
----------------
167 00000074 ; ?CSTARTUP
168 00000074 ;-----------------------------------------------
----------------
169 00000000 EXTERN __segment_init
170 00000000 EXTERN main
171 00000074 ; Initialize segments.
172 00000074 ; __segment_init is assumed to use
173 00000074 ; instruction set and to be reachable by BL from
the ICODE segment
174 00000074 ; (it is safest to link them in segment
ICODE).
175 00000074 70009FE5 ldr r0,=__segment_init
176 00000078 0FE0A0E1 mov lr, pc
177 0000007C 10FF2FE1 bx r0
178 00000080
179 00000000 PUBLIC __main
180 00000080 ?jump_to_main:
181 00000080 68E09FE5 ldr lr,=?call_exit
182 00000084 68009FE5 ldr r0,=main
183 00000088 __main:
184 00000088 10FF2FE1 bx r0
185 0000008C
186 0000008C ;-----------------------------------------------
-------------------------------
187 0000008C ;- Loop for ever
188 0000008C ;---------------
189 0000008C ;- End of application. Normally, never
occur.
190 0000008C ;- Could jump on Software Reset ( B 0x0
).
191 0000008C ;-----------------------------------------------
-------------------------------
192 0000008C ?call_exit:
193 0000008C End
194 0000008C FEFFFFEA b End
195 00000090
196 00000090 ; Never return !!
197 00000090 FDFFFFEA b End
198 00000094
199 00000094
200 00000094
201 00000094
202 00000094 ;-----------------------------------------------
----------------
203 00000094 ; Prefetch Abort Handler
204 00000094 ;-----------------------------------------------
----------------
205 00000094 ; EXTERN SEND_ASR_VALUE
206 00000094 ;Prefetch_Abort_Handler:
207 00000094 ;
208 00000094 ;- Enable Interrupt and Switch in Supervisor
Mode
209 00000094 ; msr CPSR_c, #ARM_MODE_SVC
210 00000094 ;
211 00000094 ; ldr r0,=SEND_ASR_VALUE
212 00000094 ; bx r0
213 00000094 ; Never return !!
214 00000094 ; b End
215 00000094 ;-----------------------------------------------
-------------------------------
216 00000094 ;- Manage exception
217 00000094 ;---------------
218 00000094 ;- This module The exception must be ensure in
ARM mode
219 00000094 ;-----------------------------------------------
-------------------------------
220 00000094 ;-----------------------------------------------
-------------------------------
221 00000094 ;- Function : IRQ_Handler_Entry
222 00000094 ;- Treatments : IRQ Controller
Interrupt Handler.
223 00000094 ;- Called Functions : AIC_IVR[interrupt]
224 00000094 ;-----------------------------------------------
-------------------------------
225 00000094
226 00000094 IRQ_Handler_Entry:
227 00000094
228 00000094 ;- Manage Exception Entry
229 00000094 ;- Adjust and save LR_irq in IRQ stack
230 00000094 04E04EE2 sub lr, lr, #4
231 00000098 00402DE9 stmfd sp!, {lr}
232 0000009C ;- Save and r0 in IRQ stack
233 0000009C 01002DE9 stmfd sp!, {r0}
234 000000A0
235 000000A0 ;- Write in the IVR to support Protect
Mode
236 000000A0 ;- No effect in Normal Mode
237 000000A0 ;- De-assert the NIRQ and clear the source in
Protect Mode
238 000000A0 40E09FE5 ldr r14, =AT91C_BASE_AIC
239 000000A4 00019EE5 ldr r0 , [r14, #AIC_IVR]
240 000000A8 00E18EE5 str r14, [r14, #AIC_IVR]
241 000000AC
242 000000AC ;- Enable Interrupt and Switch in Supervisor
Mode
243 000000AC 13F021E3 msr CPSR_c, #ARM_MODE_SVC
244 000000B0
245 000000B0 ;- Save scratch/used registers and LR in User
Stack
246 000000B0 0E502DE9 stmfd sp!, { r1-r3, r12,
r14}
247 000000B4
248 000000B4 ;- Branch to the routine pointed by the
AIC_IVR
249 000000B4 0FE0A0E1 mov r14, pc
250 000000B8 10FF2FE1 bx r0
251 000000BC
252 000000BC ;- Restore scratch/used registers and LR from
User Stack
253 000000BC 0E50BDE8 ldmia sp!, { r1-r3, r12,
r14}
254 000000C0
255 000000C0 ;- Disable Interrupt and switch back in IRQ
mode
256 000000C0 92F021E3 msr CPSR_c, #I_BIT |
ARM_MODE_IRQ
257 000000C4
258 000000C4 ;- Mark the End of Interrupt on the AIC
259 000000C4 1CE09FE5 ldr r14, =AT91C_BASE_AIC
260 000000C8 30E18EE5 str r14, [r14, #AIC_EOICR]
261 000000CC
262 000000CC ;- Restore SPSR_irq and r0 from IRQ stack
263 000000CC 0100BDE8 ldmia sp!, {r0}
264 000000D0
265 000000D0 ;- Restore adjusted LR_irq from IRQ stack
directly in the PC
266 000000D0 0080FDE8 ldmia sp!, {pc}^
267 000000D4
268 000000D4 ;-----------------------------------------------
----------------
269 000000D4 ; ?EXEPTION_VECTOR
270 000000D4 ; This module is only linked if needed for
closing files.
271 000000D4 ;-----------------------------------------------
----------------
272 00000000 PUBLIC AT91F_Default_FIQ_handle
r
273 00000000 PUBLIC AT91F_Default_IRQ_handle
r
274 00000000 PUBLIC AT91F_Spurious_handler
275 000000D4
276 000000D4 CODE32 ; Always ARM mode after
exeption
277 000000D4
278 000000D4 AT91F_Default_FIQ_handler
279 000000D4 FEFFFFEA b AT91F_Default_FIQ_handler
280 000000D8
281 000000D8 AT91F_Default_IRQ_handler
282 000000D8 FEFFFFEA b AT91F_Default_IRQ_handler
283 000000DC
284 000000DC AT91F_Spurious_handler
285 000000DC FEFFFFEA b AT91F_Spurious_handler
286 000000E0
287 000000E0 ENDMOD
287.1 000000E0 TABLE
287.2 000000E0 ........ Reference on line 112,149
287.3 000000E4 ........ Reference on line 114
287.4 000000E8 00F0FFFF Reference on line 154,238,259
287.5 000000EC ........ Reference on line 175
287.6 000000F0 ........ Reference on line 181
287.7 000000F4 ........ Reference on line 182
287 000000F8 ENDMOD
##############################
# CRC:F505 #
# Errors: 0 #
# Warnings: 0 #
# Bytes: 248 #
##############################
##############################
# CRC:F505 #
# Errors: 0 #
# Warnings: 0 #
# Bytes: 248 #
##############################
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