📄 dp_cfg.h
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/************************ Filename: dp_cfg.h ********************************/
/* ========================================================================= */
/* */
/* 0000 000 000 00000 0 000 0 0 0 0000 */
/* 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 */
/* 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Einsteinstra遝 6 */
/* 0000 000 0 0 000 0 0 00000 0 0000 91074 Herzogenaurach */
/* 0 00 0 0 0 0 0 0 0 0 0 */
/* 0 0 0 0 0 0 0 0 0 0 0 0 0 Tel: ++49-9132-744-200 */
/* 0 0 0 000 0 0 000 0 0 0 0 GmbH Fax: ++49-9132-744-204 */
/* */
/* ========================================================================= */
/* */
/* Function: Configuration file for VPC3+ */
/* */
/* ------------------------------------------------------------------------- */
/* */
/* Technical support: P. Fredehorst */
/* Tel. : ++49-9132/744-214 */
/* Fax. : -204 */
/* eMail: pfredehorst@profichip.com */
/* */
/*****************************************************************************/
/*****************************************************************************/
/* contents:
- compiler switches
- user defines
-
- length of buffers
- defines for MSAC2
- defines for MSAC1
- defines for ALARM
- defines for ISOCHRON
- defines for DXB PUBLISHER
- defines for DXB SUBSCRIBER
- Hardwaremode
- Interruptevents
- calculating area (do not edit this part)
*/
/*****************************************************************************/
/* reinclude protection */
#ifndef DP_CFG_H
#define DP_CFG_H
/*--------------------------------------------------------------------------*/
/* profibus services */
/*--------------------------------------------------------------------------*/
/* todo: setup required services */
/*---------------------------------------------------------------------------*/
/* User defines */
/*---------------------------------------------------------------------------*/
/* todo */
/*-----------------------------------------------------------------------*/
/* general slave parameter */
/*-----------------------------------------------------------------------*/
#define DP_ADDR ((UBYTE)0x07) // Slave address
#define IDENT_NR ((UWORD)0xADAC) // PROFIBUS Ident Number
#define USER_WD ((UWORD)0x01FF) // User Watchdog
// set watchdog greater than 0x00FF, if serial printouts used
// The UserWatchdog is only active in DataExchange. The UserWatchdog
// isn't timebased, it's a counter of DataExchange-telegrams.
/*-----------------------------------------------------------------------*/
/* define buffer length */
/*-----------------------------------------------------------------------*/
#define DIN_BUFSIZE ((UBYTE)0xF4) // Length of the DIn Buffer (Data Slave to Master) 0..244
#define DOUT_BUFSIZE ((UBYTE)0xF4) // Length of the DOut Buffer (Data Master to Slave) 0..244
#define PRM_BUFSIZE ((UBYTE)0x40) // Length of the Parameter Buffer 7..244
#define DIAG_BUFSIZE ((UBYTE)0x40) // Length of the Diagnosis Buffer 6..244
#define CFG_BUFSIZE ((UBYTE)0x40) // Length of the Configuration Buffer 1..244
#define SSA_BUFSIZE ((UBYTE)0x00) // Length of the Input Data in the Set_Slave_Address-Buffer 0 and 4..244
// 0: SetSlaveAddress will be deactivated!
/*---------------------------------------------------------------------------*/
/* set hardware modes */
/*---------------------------------------------------------------------------*/
#define DP_VPC3_4KB_MODE // (only VPC3+B, VPC3+C)
/*-----------------------------------------------------------------------*/
/* ModeRegister0 (7..0) ( page 15 ) */
/*-----------------------------------------------------------------------*/
//
// bit 7 6 5 4 3 2 1 0
// --------------------------------------------------------------------------
// | Freeze | Sync | Early | Int_Pol | MinTSDR | Res | Dis_Stop | Dis_Start |
// | supp. | supp.| RDY | | | | Control | Control |
// --------------------------------------------------------------------------
// 1 1 0 0 0 0 0 0 = 0xC0 // Default
//
#define INIT_VPC3_MODE_REG_L ((UBYTE)0xC0)
/*-----------------------------------------------------------------------*/
/* ModeRegister0 (15..8) ( page 15 ) */
/*-----------------------------------------------------------------------*/
//
// bit15 14 13 12 11 10 9 8
// ------------------------------------------------------------------------------------
// | Res | PrmCmd | Spec_Clear | Spec_Prm | SetExtPrm | User_Time | EOI_Time | DP |
// | | Supp | Mode | Buf_Mode | Supp | Base | Base | Mode |
// ------------------------------------------------------------------------------------
// 0 0 1 0 0 1 1 1 = 0x27 // Default
//
#define INIT_VPC3_MODE_REG_H ((UBYTE)0x27)
/*-----------------------------------------------------------------------*/
/* ModeRegister2 (7..0) ( page 19 ) (only VPC3+B, VPC3+C) */
/*-----------------------------------------------------------------------*/
//
// bit 7 6 5 4 3 2 1 0
// --------------------------------------------------------------------------------------
// | 4KB | No_Check | SYNC_ | SYNC_ | DX_Int_ | DX_Int_ | No_Check_ | NEW_GC_ |
// | Mode | Prm_Reserved | Pol | ENA | Port | Mode | GC_RESERVED | Int_Mode |
// --------------------------------------------------------------------------------------
// 1 0 0 0 0 0 0 1 = 0x01 or 0x81
//
#ifdef DP_VPC3_4KB_MODE
#define INIT_VPC3_MODE_REG_2 ((UBYTE)0x81)
#else
#define INIT_VPC3_MODE_REG_2 ((UBYTE)0x01)
#endif
/*---------------------------------------------------------------------------*/
/* set interrupt indications */
/*---------------------------------------------------------------------------*/
/*-----------------------------------------------------------------------*/
/* Interrupt Mask Register (7..0) ( page 23 ) */
/*-----------------------------------------------------------------------*/
// bit7 6 5 4 3 2 1 0
// ----------------------------------------------------------------------------------------
// | DXB | New_Ext | DXB_LINK | User_Timer | WD_DP | Baud_Rate | Go/Leave | MAC |
// | OUT | PRM_Data | ERROR | Clock | Mode_Timeout | detect | DataEx | Reset |
// ----------------------------------------------------------------------------------------
// 0 0 0 0 1 1 1 0 = 0xBE // Default
//
#define INIT_VPC3_IND_L 0x0E
/*-----------------------------------------------------------------------*/
/* Interrupt Mask Register (15..8) ( page 23 ) */
/*-----------------------------------------------------------------------*/
// bit 15 14 13 12 11 10 9 8
// -----------------------------------------------------------------------------------
// | REQ_PDU | POLL_END | DX_OUT | Diag_Buffer | New_PRM | NewCfg | NewSSA | NewGC |
// | Ind | Ind | | Changed | Data | Data | Data | Command |
// -----------------------------------------------------------------------------------
// 0 0 1 1 1 1 0 0 = 0x3C // Default
//
#define INIT_VPC3_IND_H 0x3C
/*---------------------------------------------------------------------------*/
/* end of user defines */
/*---------------------------------------------------------------------------*/
/*---------------------------------------------------------------------------*/
/* !!!!! do not edit this calculating part !!!!! */
/*---------------------------------------------------------------------------*/
// == Segmentation VPC3+ ===============================================================
#ifdef DP_VPC3_4KB_MODE
// 16 Byte segmentation
#define SEG_OFFSET ((UBYTE)0x0F)
#define SEG_MULDIV ((UBYTE)0x04)
#define SEG_ADDBYTE ((UWORD)0xFFF0)
#define SEG_ADDWORD ((UWORD)0xFFF0)
#else
// 8 Byte segmentation
#define SEG_OFFSET ((UBYTE)0x07)
#define SEG_MULDIV ((UBYTE)0x03)
#define SEG_ADDBYTE ((UWORD)0xF8)
#define SEG_ADDWORD ((UWORD)0xFFF8)
#endif
#define DP_ORG_LENGTH 0x40 // organizational parameter
#define SAP_LENGTH 0x10
#ifdef DP_VPC3_4KB_MODE
#define ASIC_RAM_LENGTH 0x1000
#define ASIC_USER_RAM (ASIC_RAM_LENGTH - DP_ORG_LENGTH - SAP_LENGTH)
#else
#define ASIC_RAM_LENGTH 0x800
#define ASIC_USER_RAM (ASIC_RAM_LENGTH - DP_ORG_LENGTH - SAP_LENGTH)
#endif
#define ISR_ENABLE_VPC3_INT_MAC_RESET 0
#define ISR_ENABLE_VPC3_INT_GO_LEAVE_DATA_EX 0
#define ISR_ENABLE_VPC3_INT_BAUDRATE_DETECT 0
#define ISR_ENABLE_VPC3_INT_WD_DP_TIMEOUT 0
#define ISR_ENABLE_VPC3_INT_USER_TIMER_CLOCK 0
#define ISR_ENABLE_VPC3_INT_DXB_LINK_ERROR 0
#define ISR_ENABLE_VPC3_INT_NEW_EXT_PRM_DATA 0
#define ISR_ENABLE_VPC3_INT_DXB_OUT 0
#define ISR_ENABLE_VPC3_INT_NEW_GC_COMMAND 0
#define ISR_ENABLE_VPC3_INT_NEW_SSA_DATA 0
#define ISR_ENABLE_VPC3_INT_NEW_CFG_DATA 0
#define ISR_ENABLE_VPC3_INT_NEW_PRM_DATA 0
#define ISR_ENABLE_VPC3_INT_DIAG_BUF_CHANGED 0
#define ISR_ENABLE_VPC3_INT_DX_OUT 0
#define ISR_ENABLE_VPC3_INT_RESERVED 0
#define ISR_ENABLE_VPC3_INT_SERVICE_ERROR 0
#if( INIT_VPC3_IND_L & 0x01 )
#undef ISR_ENABLE_VPC3_INT_MAC_RESET
#define ISR_ENABLE_VPC3_INT_MAC_RESET 1
#endif
#if( INIT_VPC3_IND_L & 0x02 )
#undef ISR_ENABLE_VPC3_INT_GO_LEAVE_DATA_EX
#define ISR_ENABLE_VPC3_INT_GO_LEAVE_DATA_EX 1
#endif
#if( INIT_VPC3_IND_L & 0x04 )
#undef ISR_ENABLE_VPC3_INT_BAUDRATE_DETECT
#define ISR_ENABLE_VPC3_INT_BAUDRATE_DETECT 1
#endif
#if( INIT_VPC3_IND_L & 0x08 )
#undef ISR_ENABLE_VPC3_INT_WD_DP_TIMEOUT
#define ISR_ENABLE_VPC3_INT_WD_DP_TIMEOUT 1
#endif
#if( INIT_VPC3_IND_L & 0x10 )
#undef ISR_ENABLE_VPC3_INT_USER_TIMER_CLOCK
#define ISR_ENABLE_VPC3_INT_USER_TIMER_CLOCK 1
#endif
#if( INIT_VPC3_IND_L & 0x20 )
#undef ISR_ENABLE_VPC3_INT_DXB_LINK_ERROR
#define ISR_ENABLE_VPC3_INT_DXB_LINK_ERROR 1
#endif
#if( INIT_VPC3_IND_L & 0x40 )
#undef ISR_ENABLE_VPC3_INT_NEW_EXT_PRM_DATA
#define ISR_ENABLE_VPC3_INT_NEW_EXT_PRM_DATA 1
#endif
#if( INIT_VPC3_IND_L & 0x80 )
#undef ISR_ENABLE_VPC3_INT_DXB_OUT
#define ISR_ENABLE_VPC3_INT_DXB_OUT 1
#endif
#if( INIT_VPC3_IND_H & 0x01 )
#undef ISR_ENABLE_VPC3_INT_NEW_GC_COMMAND
#define ISR_ENABLE_VPC3_INT_NEW_GC_COMMAND 1
#endif
#if( INIT_VPC3_IND_H & 0x02 )
#undef ISR_ENABLE_VPC3_INT_NEW_SSA_DATA
#define ISR_ENABLE_VPC3_INT_NEW_SSA_DATA 1
#endif
#if( INIT_VPC3_IND_H & 0x04 )
#undef ISR_ENABLE_VPC3_INT_NEW_CFG_DATA
#define ISR_ENABLE_VPC3_INT_NEW_CFG_DATA 1
#endif
#if( INIT_VPC3_IND_H & 0x08 )
#undef ISR_ENABLE_VPC3_INT_NEW_PRM_DATA
#define ISR_ENABLE_VPC3_INT_NEW_PRM_DATA 1
#endif
#if( INIT_VPC3_IND_H & 0x10 )
#undef ISR_ENABLE_VPC3_INT_DIAG_BUF_CHANGED
#define ISR_ENABLE_VPC3_INT_DIAG_BUF_CHANGED 1
#endif
#if( INIT_VPC3_IND_H & 0x20 )
#undef ISR_ENABLE_VPC3_INT_DX_OUT
#define ISR_ENABLE_VPC3_INT_DX_OUT 1
#endif
#if( INIT_VPC3_IND_H & 0x40 )
#undef ISR_ENABLE_VPC3_INT_POLL_END_IND
#define ISR_ENABLE_VPC3_INT_POLL_END_IND 1
#endif
#if( INIT_VPC3_IND_H & 0x80 )
#undef ISR_ENABLE_VPC3_INT_FDL_IND
#define ISR_ENABLE_VPC3_INT_FDL_IND 1
#endif
/*****************************************************************************/
/* reinclude-protection */
#else
#pragma message "The header DP_CFG.H is included twice or more !"
#endif
/*****************************************************************************/
/* Copyright (C) profichip GmbH 2004. Confidential. */
/*****************************************************************************/
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