jit3-i386.def

基于LWVCL开发的库

		debug(("fldl %d(ebp)\n", or));
	}
}

/* --------------------------------------------------------------------- */

define_insn(add_int, add_RRR)
{
	int r;
	int w;

	debug(("instr\t%s\n",__PRETTY_FUNCTION__));

	check_reg_01();

	r = rreg_int(2);
	w = rwreg_int(0);

	OUT(0x01);
        OUT(0xC0|(r<<3)|w);

	debug(("addl %s,%s\n", regname(r), regname(w)));
}

define_insn(adc_int, adc_RRR)
{
	int r;
	int w;

	debug(("instr\t%s\n",__PRETTY_FUNCTION__));

	r = rreg_int(2);
	w = rwreg_int(0);

	OUT(0x11);
        OUT(0xC0|(r<<3)|w);

	debug(("adcl %s,%s\n", regname(r), regname(w)));
}

define_insn(add_float, fadd_RRR)
{
	int rr, rm;

	debug(("instr\t%s\n",__PRETTY_FUNCTION__));

	/*
	 * XXX Order is important here...  If we put slot 2 into memory and
	 * slot 1 into the register we get a whole bunch of excess
	 * spills/reloaeds.
	 */
	rm = rslot_float(1);	/* Get slot 1 into memory */
	rr = rreg_float(2);	/* Load slot 2 into the register stack */
	wreg_float(0);		/* Result will be in register stack */

	OUT(0xD8);
	OUT(0x80|REG_ebp);
	LOUT(rm);

	debug(("fadd %d(ebp)\n", rm));
}

define_insn(add_double, faddl_RRR)
{
	int rr, rm;

	debug(("instr\t%s\n",__PRETTY_FUNCTION__));

	rm = rslot_double(1);	/* Get slot 1 into memory */
	rr = rreg_double(2);	/* Load slot 2 into the register stack */
	wreg_double(0);		/* Result will be in register stack */

	OUT(0xDC);
	OUT(0x80|REG_ebp);
	LOUT(rm);

	debug(("faddl %d(ebp)\n", rm));
}

define_insn(sub_int, sub_RRR)
{
	int r;
	int w;

	debug(("instr\t%s\n",__PRETTY_FUNCTION__));

	check_reg_01();

	r = rreg_int(2);
	w = rwreg_int(0);

	OUT(0x29);
        OUT(0xC0|(r<<3)|w);

	debug(("subl %s,%s\n", regname(r), regname(w)));
}

define_insn(sbc_int, sbc_RRR)
{
	int r;
	int w;

	debug(("instr\t%s\n",__PRETTY_FUNCTION__));

	r = rreg_int(2);
	w = rwreg_int(0);

	OUT(0x19);
        OUT(0xC0|(r<<3)|w);

	debug(("sbbl %s,%s\n", regname(r), regname(w)));
}

define_insn(sub_float, fsub_RRR)
{
	int rr, rm;

	debug(("instr\t%s\n",__PRETTY_FUNCTION__));

	rm = rslot_float(1);	/* Get slot 1 into memory */
	rr = rreg_float(2);	/* Load slot 2 into the register stack */
	wreg_float(0);		/* Result will be in register stack */

	OUT(0xD8);
	OUT(0xA8|REG_ebp);
	LOUT(rm);

	debug(("fsub %d(ebp)\n", rm));
}

define_insn(sub_double, fsubl_RRR)
{
	int rr, rm;

	debug(("instr\t%s\n",__PRETTY_FUNCTION__));

	rm = rslot_double(1);	/* Get slot 1 into memory */
	rr = rreg_double(2);	/* Load slot 2 into the register stack */
	wreg_double(0);		/* Result will be in register stack */

	OUT(0xDC);
	OUT(0xA8|REG_ebp);
	LOUT(rm);

	debug(("fsubl %d(ebp)\n", rm));
}

define_insn(neg_float, negf_RxR)
{
	debug(("instr\t%s\n",__PRETTY_FUNCTION__));

	rreg_float(2);
	wreg_float(0);

	OUT(0xD9);
	OUT(0xe0);

	debug(("fchs\n"));
}

define_insn(neg_double, negd_RxR)
{
	debug(("instr\t%s\n",__PRETTY_FUNCTION__));

	rreg_double(2);
	wreg_double(0);

	OUT(0xD9);
	OUT(0xe0);

	debug(("fchsl\n"));
}

define_insn(mul_int, mul_RRR)
{
	int r;
	int w;

	debug(("instr\t%s\n",__PRETTY_FUNCTION__));

	check_reg_01();

	r = rreg_int(2);
	w = rwreg_int(0);

	OUT(0x0F);
	OUT(0xAF);
        OUT(0xC0|(w<<3)|r);

	debug(("imull %s,%s\n", regname(r), regname(w)));
}

define_insn(mul_float, fmul_RRR)
{
	int rr, rm;

	debug(("instr\t%s\n",__PRETTY_FUNCTION__));

	rm = rslot_float(1);	/* Get slot 1 into memory */
	rr = rreg_float(2);	/* Load slot 2 into the register stack */
	wreg_float(0);		/* Result will be in register stack */

	OUT(0xD8);
	OUT(0x88|REG_ebp);
	LOUT(rm);

	debug(("fmul %d(ebp)\n", rm));
}

define_insn(mul_double, fmull_RRR)
{
	int rr, rm;

	debug(("instr\t%s\n",__PRETTY_FUNCTION__));

	rm = rslot_double(1);	/* Get slot 1 into memory */
	rr = rreg_double(2);	/* Load slot 2 into the register stack */
	wreg_double(0);		/* Result will be in register stack */

	OUT(0xDC);
	OUT(0x88|REG_ebp);
	LOUT(rm);

	debug(("fmull %d(ebp)\n", rm));
}

define_insn(div_int, div_RRR)
{
	int r;
	int w;
	label *l1;

	debug(("instr\t%s\n",__PRETTY_FUNCTION__));

	check_reg_01();

	w = rwreg_int(0);

	/* Can only divide accumulator. */
	force_move_int(seq_slot(s, 0), REG_eax, w);

	/* EDX is also used so get hold of it */
	clobberRegister(REG_edx);

	r = rreg_int(2);

	assert(r != REG_eax);
	assert(r != REG_edx);

	/* special case for LONG_MIN / -1l: r == -1 ? -eax : eax / r  */
	OUT(0x83);
	OUT(0xF8|r);
	OUT(0xFF);
	debug(("cmp #0xFF,%s\n", regname(r)));

	l1 = KaffeJIT3_newLabel();
	l1->type = Linternal| Llong8|Lrelative;
	OUT(0x74);
	l1->at = CODEPC;
	OUT(0);
	l1->from = CODEPC;
	debug(("je neg\n"));

	/* Setup EDX - should contains the sign of EAX */
	do_move_int(REG_edx, REG_eax);
	OUT(0x99);
	debug(("cltd\n"));

	OUT(0xF7);
        OUT(0xF8|r);
	debug(("idivl %s,%s\n", regname(r), regname(w)));

	OUT(0xEB);
	OUT(2);
	debug(("jmp +2\n"));

	debug(("neg:\n"));
	l1->to = CODEPC;
	OUT(0xF7);
	OUT(0xD8|REG_eax);
	debug(("neg eax\n"));
}

define_insn(div_float, fdiv_RRR)
{
	int rr, rm;

	debug(("instr\t%s\n",__PRETTY_FUNCTION__));

	rm = rslot_float(1);	/* Get slot 1 into memory */
	rr = rreg_float(2);	/* Load slot 2 into the register stack */
	wreg_float(0);		/* Result will be in register stack */

	OUT(0xD8);
	OUT(0xB8|REG_ebp);
	LOUT(rm);

	debug(("fdiv %d(ebp)\n", rm));
}

define_insn(div_double, fdivl_RRR)
{
	int rr, rm;

	debug(("instr\t%s\n",__PRETTY_FUNCTION__));

	rm = rslot_double(1);	/* Get slot 1 into memory */
	rr = rreg_double(2);	/* Load slot 2 into the register stack */
	wreg_double(0);		/* Result will be in register stack */

	OUT(0xDC);
	OUT(0xB8|REG_ebp);
	LOUT(rm);

	debug(("fdivl %d(ebp)\n", rm));
}

define_insn(rem_int, rem_RRR)
{
	int r;
	int w;
	label *l1;

	debug(("instr\t%s\n",__PRETTY_FUNCTION__));

	check_reg_01();

	w = rwreg_int(0);

	/* Can only divide accumulator. */
	force_move_int(seq_slot(s, 0), REG_eax, w);

	/* EDX is also used so get hold of it */
	clobberRegister(REG_edx);

	r = rreg_int(2);

	assert(r != REG_eax);
	assert(r != REG_edx);

	/* special case for LONG_MIN % -1l: r == -1 ? 0 : eax / r  */
	OUT(0x83);
	OUT(0xF8|r);
	OUT(0xFF);
	debug(("cmp #0xFF,%s\n", regname(r)));

	l1 = KaffeJIT3_newLabel();
	l1->type = Linternal| Llong8|Lrelative;
	OUT(0x74);
	l1->at = CODEPC;
	OUT(0);
	l1->from = CODEPC;
	debug(("je const0\n"));

	/* Setup EDX - should contains the sign of EAX */
	do_move_int(REG_edx, REG_eax);
	OUT(0x99);
	debug(("cltd\n"));

	OUT(0xF7);
        OUT(0xF8|r);
	debug(("idivl %s,%s\n", regname(r), regname(w)));

	OUT(0xEB);
	OUT(2);
	debug(("jmp +2\n"));

	debug(("const0:\n"));
	l1->to = CODEPC;
	OUT(0x31);
        OUT(0xC0|(REG_edx<<3)|REG_edx);
	debug(("xorl edx,edx\n"));

	/* Result is in EDX not EAX - we must force the slot register */
	set_slot_register(seq_dst(s), REG_edx, Rint);
}

/* --------------------------------------------------------------------- */

define_insn(and_int, and_RRR)
{
	int r;
	int w;

	debug(("instr\t%s\n",__PRETTY_FUNCTION__));

	check_reg_01();

	r = rreg_int(2);
	w = rwreg_int(0);

	OUT(0x21);
        OUT(0xC0|(r<<3)|w);

	debug(("andl %s,%s\n", regname(r), regname(w)));
}

define_insn(or_int, or_RRR)
{
	int r;
	int w;

	debug(("instr\t%s\n",__PRETTY_FUNCTION__));

	check_reg_01();

	r = rreg_int(2);
	w = rwreg_int(0);

	OUT(0x09);
        OUT(0xC0|(r<<3)|w);

	debug(("orl %s,%s\n", regname(r), regname(w)));
}

define_insn(xor_int, xor_RRR)
{
	int r;
	int w;

	debug(("instr\t%s\n",__PRETTY_FUNCTION__));

	check_reg_01();

	r = rreg_int(2);
	w = rwreg_int(0);

	OUT(0x31);
        OUT(0xC0|(r<<3)|w);

	debug(("xorl %s,%s\n", regname(r), regname(w)));
}

define_insn(ashr_int, ashr_RRR)
{
	int r;
	int w;

	debug(("instr\t%s\n",__PRETTY_FUNCTION__));

	check_reg_01();

	r = rreg_ideal_int(2, REG_ecx);

	/* Can only shift by ECX. */
	safe_move_int(REG_ecx, r);

	w = rwreg_int(0);

	OUT(0xD3);
        OUT(0xF8|w);

	debug(("sarl %s,%s\n", regname(r), regname(w)));
}

define_insn(lshr_int, lshr_RRR)
{
	int r;
	int w;

	debug(("instr\t%s\n",__PRETTY_FUNCTION__));

	check_reg_01();

	r = rreg_ideal_int(2, REG_ecx);

	/* Can only shift by ECX. */
	safe_move_int(REG_ecx, r);

	w = rwreg_int(0);

	OUT(0xD3);
        OUT(0xE8|w);

	debug(("shrl %s,%s\n", regname(r), regname(w)));
}

define_insn(lshl_int, lshl_RRR)
{
	int r;
	int w;

	debug(("instr\t%s\n",__PRETTY_FUNCTION__));

	check_reg_01();

	r = rreg_ideal_int(2, REG_ecx);

	/* Can only shift by ECX. */
	safe_move_int(REG_ecx, r);

	w = rwreg_int(0);

	OUT(0xD3);
        OUT(0xE0|w);

	debug(("shll %s,%s\n", regname(r), regname(w)));
}

/* --------------------------------------------------------------------- */

define_insn(load_int, load_RxR)
{
	int r = rreg_int(2);
	int w = wreg_int(0);

	debug(("instr\t%s\n",__PRETTY_FUNCTION__));

	OUT(0x8B);
	OUT(0x00|(w<<3)|r);
	if (r == REG_esp) {
		OUT(0x20|REG_esp);
	}

	debug(("movl (%s),%s\n", regname(r), regname(w)));
}

define_insn(load_float, fload_RxR)
{
	int r;

	debug(("instr\t%s\n",__PRETTY_FUNCTION__));

	r = rreg_int(2);
	wreg_float(0);

	OUT(0xD9);
	OUT(0x00|r);

	debug(("fld (%s)\n", regname(r)));
}

define_insn(load_double, floadl_RxR)
{
	int r;

	debug(("instr\t%s\n",__PRETTY_FUNCTION__));

	r = rreg_int(2);
	wreg_double(0);

	OUT(0xDD);
	OUT(0x00|r);

	debug(("fldl (%s)\n", regname(r)));
}

define_insn(store_int, store_xRR)
{
	int r = rreg_int(2);
	int w = rreg_int(1);

	debug(("instr\t%s\n",__PRETTY_FUNCTION__));

	OUT(0x89);
	OUT(0x00|(r<<3)|w);
	if (w == REG_esp) {
		OUT(0x20|REG_esp);
	}

	debug(("movl %s,(%s)\n", regname(r), regname(w)));
}

define_insn(store_float, fstore_RxR)
{
	int w;

	debug(("instr\t%s\n",__PRETTY_FUNCTION__));

	rreg_float(2);
	w = rreg_int(1);
	
	OUT(0xD9);
	OUT(0x18|w);

	debug(("fstp (%s)\n", regname(w)));
}

define_insn(store_double, fstorel_RxR)
{
	int w;

	debug(("instr\t%s\n",__PRETTY_FUNCTION__));

	rreg_double(2);
	w = rreg_int(1);

	OUT(0xDD);
	OUT(0x18|w);

	debug(("fstlp (%s)\n", regname(w)));
}

/* --------------------------------------------------------------------- */

define_insn(cmp_int, cmp_xRR)
{
	int r1 = rreg_int(1);
	int r2 = rreg_int(2);

	debug(("instr\t%s\n",__PRETTY_FUNCTION__));

	OUT(0x39);
	OUT(0xC0|(r2<<3)|r1);

	debug(("cmpl %s,%s\n", regname(r2), regname(r1)));
}

/* --------------------------------------------------------------------- */

define_insn(cvt_int_float, cvtif_RxR)
{
	int r;

	debug(("instr\t%s\n",__PRETTY_FUNCTION__));

	r = rslot_int(2);
	wreg_float(0);

	OUT(0xDB);
	OUT(0x80|REG_ebp);
	LOUT(r);

	debug(("fild %d(ebp)\n", r));
}

define_insn(cvt_int_double, cvtid_RxR)
{
	int r;

	debug(("instr\t%s\n",__PRETTY_FUNCTION__));

	r = rslot_int(2);
	wreg_double(0);

	OUT(0xDB);
	OUT(0x80|REG_ebp);
	LOUT(r);

	debug(("fild %d(ebp)\n", r));
}

define_insn(cvt_float_double, cvtfd_RxR)
{
	int o = rslot_float(2);

	debug(("instr\t%s\n",__PRETTY_FUNCTION__));

	wreg_double(0);

	OUT(0xD9);
	OUT(0x80|REG_ebp);