jit-m68k.def

基于LWVCL开发的库

/* jit-m68k.def
 * M68000 instruction definition.
 *
 * Copyright (c) 1996, 1997
 *	Transvirtual Technologies, Inc.  All rights reserved.
 *
 * Copyright (c) 2004
 *	Kaffe.org contributors, see ChangeLogs for details.  All rights reserved.
 *
 * See the file "license.terms" for information on usage and redistribution 
 * of this file. 
 */

#define	KAFFE_VMDEBUG

#include <assert.h>
#include <string.h>
#include "classMethod.h"
#include "access.h"
#include "gtypes.h"
#if defined(JIT3)
#include "soft.h"
#endif

#define	REG_d0			0
#define	REG_d1			1
#define REG_a0			8
#define REG_fp			14
#define REG_sp			15
#define REG_fp0			16

#ifdef KAFFE_VMDEBUG
static const char * const rnames[] = {
	"%d0", "%d1", "%d2", "%d3", "%d4", "%d5", "%d6", "%d7",
	"%a0", "%a1", "%a2", "%a3", "%a4", "%a5", "%fp", "%sp",
	"%fp0", "%fp1", "%fp2", "%fp3", "%fp4", "%fp5", "%fp6", "%fp7",
};
#define	regname(n)	rnames[n]
#endif

#define assert_dreg(x)	assert(x >= 0 && x <= 7)
#define assert_areg(x)	assert(x >= 8 && x <= 15)
#define assert_freg(x)	assert(x >= 16 && x <= 23)
#define assert_s8(x)	assert(x >= -0x80 && x < 0x80)
#define assert_s16(x)	assert(x >= -0x8000 && x < 0x8000)

#define LSLOT(s)	((s)+1)
#define HSLOT(s)	(s)

/* FIXME -- detecting 68040 properly lets us do fp to IEEE spec.  */
#define is_68040	0

/* --------------------------------------------------------------------- */
/* Instruction assembly */

/* Here we make implementing the instructions a bit easier, but calling
   them slightly more difficult, by sending specific modes to each insn
   variant.  These are encoded in the suffix of the function name like so:

	d	data register
	a	address register
	f	floating point register
	i	immediate
	I	address register indirect
	o	address register indirect with displacement
	p	address register indirect with predecrement
	x	address register indirect with index & 8-bit displacement
*/

#ifdef KAFFE_VMDEBUG
int jit_debug = 0;
#define	debug(x)	(jit_debug ? printf("%x:\t", (int)CODEPC), printf x : 0)
#else
#define	debug(x)	((void)0)
#endif


#define MODE_d		0
#define MODE_a		1
#define MODE_ind	2
#define MODE_postinc	3
#define MODE_predec	4
#define MODE_inddisp	5
#define MODE_index	6
#define MODE_src_imm	074
#define MODE_src_absw	070
#define MODE_src_absl	071

#define OPMODE_s	(is_68040 ? 0x40 : 0)
#define OPMODE_d	(is_68040 ? 0x44 : 0)

#define COPROCID	1


static inline void
op_addl_id(int imm, int dst)
{
	debug(("addl #%d, %s\n", imm, regname(dst)));
	assert_dreg(dst);
	WOUT(0xD080 | (dst << 9) | MODE_src_imm);
	LOUT(imm);
}

static inline void
op_addl_dd(int src, int dst)
{
	debug(("addl %s, %s\n", regname(src), regname(dst)));
	assert_dreg(src);
	assert_dreg(dst);
	WOUT(0xD080 | (dst << 9) | (MODE_d << 3) | (src & 7));
}

#if !defined(HAVE_NO_ADDAW)
static inline void
op_addaw_ia(int imm, int dst)
{
	debug(("addaw #%d, %s\n", imm, regname(dst)));
	assert_s16(imm);
	assert_areg(dst);
	WOUT(0xD0C0 | ((dst & 7) << 9) | MODE_src_imm);
	WOUT(imm);
}
#endif

static inline void
op_addal_ia(int imm, int dst)
{
	debug(("addal #%d, %s\n", imm, regname(dst)));
	assert_areg(dst);
	WOUT(0xD1C0 | ((dst & 7) << 9) | MODE_src_imm);
	LOUT(imm);
}

static inline void
op_addal_da(int src, int dst)
{
	debug(("addal %s, %s\n", regname(src), regname(dst)));
	assert_dreg(src);
	assert_areg(dst);
	WOUT(0xD1C0 | ((dst & 7) << 9) | (MODE_d << 3) | (src & 7));
}

static inline void
op_addql_ia(int imm, int dst)
{
	debug(("addql #%d, %s\n", imm, regname(dst)));
	assert(imm >= 1 && imm <= 8);
	assert_areg(dst);
	WOUT(0x5080 | ((imm & 7) << 9) | (MODE_a << 3) | (dst & 7));
}

static inline void
op_addql_id(int imm, int dst)
{
	debug(("addql #%d, %s\n", imm, regname(dst)));
	assert(imm >= 1 && imm <= 8);
	assert_dreg(dst);
	WOUT(0x5080 | ((imm & 7) << 9) | (MODE_d << 3) | (dst & 7));
}

static inline void
op_addxl_dd(int src, int dst)
{
	debug(("addxl %s, %s\n", regname(src), regname(dst)));
	assert_dreg(src);
	assert_dreg(dst);
	WOUT(0xD180 | (dst << 9) | src);
}

static inline void
op_andl_id(int imm, int dst)
{
	debug(("andl #0x%x, %s\n", imm, regname(dst)));
	assert_dreg(dst);
	WOUT(0xC080 | (dst << 9) | MODE_src_imm);
	LOUT(imm);
}

static inline void
op_andl_dd(int src, int dst)
{
	debug(("andl %s, %s\n", regname(src), regname(dst)));
	assert_dreg(src);
	assert_dreg(dst);
	WOUT(0xC080 | (dst << 9) | (MODE_d << 3) | (src & 7));
}

static inline void
op_asr_id(int imm, int dst)
{
	debug(("asr #%d, %s\n", imm, regname(dst)));
	assert_dreg(dst);
	assert(imm >= 1 && imm <= 8);
	WOUT(0xE080 | ((imm & 7) << 9) | dst);
}

static inline void
op_asr_dd(int src, int dst)
{
	debug(("asr %s, %s\n", regname(src), regname(dst)));
	assert_dreg(src);
	assert_dreg(dst);
	WOUT(0xE0A0 | ((src & 7) << 9) | dst);
}

static inline void
op_blo_16(int disp)
{
	debug(("blo %+d\n", disp));
	WOUT(0x6500);
	WOUT(disp);
}

#if defined(HAVE_NO_LONG_BRANCHES)

static inline void
op_beq_16(int disp)
{
	debug(("beq %+d\n", disp));
	WOUT(0x6700);
	WOUT(disp);
}

static inline void
op_bne_16(int disp)
{
	debug(("bne %+d\n", disp));
	WOUT(0x6600);
	WOUT(disp);
}

static inline void
op_blt_16(int disp)
{
	debug(("blt %+d\n", disp));
	WOUT(0x6D00);
	WOUT(disp);
}

static inline void
op_ble_16(int disp)
{
	debug(("ble %+d\n", disp));
	WOUT(0x6F00);
	WOUT(disp);
}

static inline void
op_bgt_16(int disp)
{
	debug(("bgt %+d\n", disp));
	WOUT(0x6E00);
	WOUT(disp);
}

static inline void
op_bge_16(int disp)
{
	debug(("bge %+d\n", disp));
	WOUT(0x6C00);
	WOUT(disp);
}

static inline void
op_bra_16(int disp)
{
	debug(("bra %+d\n", disp));
	WOUT(0x6000);
	WOUT(disp);
}

#else

static inline void
op_beq_32(int disp)
{
	debug(("beq %+d\n", disp));
	WOUT(0x67FF);
	LOUT(disp);
}

static inline void
op_bne_32(int disp)
{
	debug(("bne %+d\n", disp));
	WOUT(0x66FF);
	LOUT(disp);
}

static inline void
op_blt_32(int disp)
{
	debug(("blt %+d\n", disp));
	WOUT(0x6DFF);
	LOUT(disp);
}

static inline void
op_ble_32(int disp)
{
	debug(("ble %+d\n", disp));
	WOUT(0x6FFF);
	LOUT(disp);
}

static inline void
op_bgt_32(int disp)
{
	debug(("bgt %+d\n", disp));
	WOUT(0x6EFF);
	LOUT(disp);
}

static inline void
op_bge_32(int disp)
{
	debug(("bge %+d\n", disp));
	WOUT(0x6CFF);
	LOUT(disp);
}

static inline void
op_blo_32(int disp)
{
	debug(("blo %+d\n", disp));
	WOUT(0x65FF);
	LOUT(disp);
}

static inline void
op_bra_32(int disp)
{
	debug(("bra %+d\n", disp));
	WOUT(0x60FF);
	LOUT(disp);
}
#endif

static inline void
op_bsr_32(int disp)
{
	debug(("bsr %+d\n", disp));
	WOUT(0x61FF);
	LOUT(disp);
}

static inline void
op_clrl_d(int dst)
{
	debug(("clrl %s\n", regname(dst)));
	assert_dreg(dst);
	WOUT(0x4280 | (MODE_d << 3) | (dst & 7));
}

static inline void
op_cmpl_dd(int src1, int src2)
{
	debug(("cmpl %s, %s\n", regname(src1), regname(src2)));
	assert_dreg(src1);
	assert_dreg(src2);
	WOUT(0xB080 | (src2 << 9) | (MODE_d << 7) | (src1 & 7));
}

static inline void
op_cmpal_aa(int src1, int src2)
{
	debug(("cmpl %s, %s\n", regname(src1), regname(src2)));
	assert_areg(src1);
	assert_areg(src2);
	WOUT(0xB1C0 | (src2 << 9) | (MODE_a << 3) | (src1 & 7));
}

static inline void
op_cmpil_ia(int imm, int src2)
{
	debug(("cmpil #%d, %s\n", imm, regname(src2)));
	assert_areg(src2);
	WOUT(0x0C80 | (MODE_a << 3) | (src2 & 7));
	LOUT(imm);
}

static inline void
op_cmpil_id(int imm, int src2)
{
	debug(("cmpil #%d, %s\n", imm, regname(src2)));
	assert_dreg(src2);
	WOUT(0x0C80 | (MODE_d << 3) | (src2 & 7));
	LOUT(imm);
}

static inline void
op_divsl_ddd(int src, int r, int q)
{
	debug(("divsl %s, %s:%s\n", regname(src), regname(r), regname(q)));
	assert_dreg(src);
	assert_dreg(r);
	assert_dreg(q);
	WOUT(0x4C40 | (MODE_d << 3) | (src & 7));
	WOUT(0x0800 | (q << 12) | r);
}

static inline void
op_eorl_dd(int src, int dst)
{
	debug(("eorl %s, %s\n", regname(src), regname(dst)));
	assert_dreg(src);
	assert_dreg(dst);
	WOUT(0xB180 | ((src & 7) << 9) | (MODE_d << 3) | (dst & 7));
}

static inline void
op_extbl_d(int dst)
{
	debug(("extbl %s\n", regname(dst)));
	assert_dreg(dst);
	WOUT(0x49C0 | dst);
}

static inline void
op_extwl_d(int dst)
{
	debug(("extwl %s\n", regname(dst)));
	assert_dreg(dst);
	WOUT(0x48C0 | dst);
}

static inline void
op_exg_aa(int r1, int r2)
{
	debug(("exg %s, %s\n", regname(r1), regname(r2)));
	assert_areg(r1);
	assert_areg(r2);
	WOUT(0xC148 | ((r1 & 7) << 9) | (r2 & 7));
}

static inline void
op_exg_da(int r1, int r2)
{
	debug(("exg %s, %s\n", regname(r1), regname(r2)));
	assert_dreg(r1);
	assert_areg(r2);
	WOUT(0xC188 | (r1 << 9) | (r2 & 7));
}

static inline void
op_exg_dd(int r1, int r2)
{
	debug(("exg %s, %s\n", regname(r1), regname(r2)));
	assert_dreg(r1);
	assert_dreg(r2);
	WOUT(0xC140 | (r1 << 9) | r2);
}

static inline void
op_jmp_I(int dst)
{
	debug(("jmp (%s)\n", regname(dst)));
	assert_areg(dst);
	WOUT(0x4EC0 | (MODE_ind << 3) | (dst & 7));
}

static inline void
op_jsr_I(int dst)
{
	debug(("jsr (%s)\n", regname(dst)));
	assert_areg(dst);
	WOUT(0x4E80 | (MODE_ind << 3) | (dst & 7));
}

static inline void
op_linkw_ai(int areg, int disp)
{
	debug(("linkw %s, #%d\n", regname(areg), disp));
	assert_s16(disp);
	assert_areg(areg);
	WOUT(0x4E50 | (areg & 7));
	WOUT(disp);
}

static inline void
op_lsl_id(int imm, int dst)
{
	debug(("lsl #%d, %s\n", imm, regname(dst)));
	assert_dreg(dst);
	assert(imm >= 1 && imm <= 8);
	WOUT(0xE188 | ((imm & 7) << 9) | dst);
}

static inline void
op_lsl_dd(int src, int dst)
{
	debug(("lsl %s, %s\n", regname(src), regname(dst)));
	assert_dreg(src);
	assert_dreg(dst);
	WOUT(0xE1A8 | ((src & 7) << 9) | dst);
}

static inline void
op_lsr_id(int imm, int dst)
{
	debug(("lsr #%d, %s\n", imm, regname(dst)));
	assert_dreg(dst);
	assert(imm >= 1 && imm <= 8);
	WOUT(0xE088 | ((imm & 7) << 9) | dst);
}

static inline void
op_lsr_dd(int src, int dst)
{
	debug(("lsr %s, %s\n", regname(src), regname(dst)));
	assert_dreg(src);
	assert_dreg(dst);
	WOUT(0xE0A8 | ((src & 7) << 9) | dst);
}

static inline void
op_moveb_Id(int src, int dst)
{
	debug(("moveb (%s), %s\n", regname(src), regname(dst)));
	assert_areg(src);
	assert_dreg(dst);
	WOUT(0x1000 | ((dst & 7) << 9) | (MODE_d << 6) | (MODE_ind << 3) | (src & 7));
}

static inline void
op_moveb_dI(int src, int dst)
{
	debug(("moveb %s, (%s)\n", regname(src), regname(dst)));
	assert_dreg(src);
	assert_areg(dst);
	WOUT(0x1000 | ((dst & 7) << 9) | (MODE_ind << 6) | (MODE_d << 3) | (src & 7));
}

static inline void
op_movew_Id(int src, int dst)
{
	debug(("movew (%s), %s\n", regname(src), regname(dst)));
	assert_areg(src);
	assert_dreg(dst);
	WOUT(0x3000 | ((dst & 7) << 9) | (MODE_d << 6) | (MODE_ind << 3) | (src & 7));
}

static inline void
op_movew_dI(int src, int dst)
{
	debug(("movew %s, (%s)\n", regname(src), regname(dst)));
	assert_dreg(src);
	assert_areg(dst);
	WOUT(0x3000 | ((dst & 7) << 9) | (MODE_ind << 6) | (MODE_d << 3) | (src & 7));
}

static inline void
op_movel_ao(int src, int base, int disp)
{
	debug(("movel %s, %d(%s)\n", regname(src), disp, regname(base)));
	assert_areg(src);
	assert_areg(base);
	assert_s16(disp);
	WOUT(0x2000 | ((base & 7) << 9) | (MODE_inddisp << 6) | (MODE_a << 3) | (src & 7));
	WOUT(disp);
}

static inline void
op_movel_ad(int src, int dst)
{
	debug(("movel %s, %s\n", regname(src), regname(dst)));
	assert_areg(src);
	assert_dreg(dst);
	WOUT(0x2000 | ((dst & 7) << 9) | (MODE_d << 6) | (MODE_a << 3) | (src & 7));
}

#if defined(JIT3)
static inline void
op_movel_da(int src, int dst)
{
	debug(("movel %s, %s\n", regname(src), regname(dst)));
	assert_areg(src);
	assert_dreg(dst);
	WOUT(0x2000 | ((dst & 7) << 9) | (MODE_a << 6) | (MODE_d << 3) | (src & 7));
}
#endif

static inline void
op_movel_dd(int src, int dst)
{
	debug(("movel %s, %s\n", regname(src), regname(dst)));
	assert_dreg(src);
	assert_dreg(dst);
	WOUT(0x2000 | ((dst & 7) << 9) | (MODE_d << 6) | (MODE_d << 3) | (src & 7));
}

static inline void
op_movel_do(int src, int base, int disp)
{
	debug(("movel %s, %d(%s)\n", regname(src), disp, regname(base)));
	assert_dreg(src);
	assert_areg(base);
	assert_s16(disp);
	WOUT(0x2000 | ((base & 7) << 9) | (MODE_inddisp << 6) | (MODE_d << 3) | (src & 7));
	WOUT(disp);
}

static inline void
op_movel_id(int imm, int dst)
{
	debug(("movel #%d, %s\n", imm, regname(dst)));
	assert_dreg(dst);
	WOUT(0x2000 | ((dst & 7) << 9) | (MODE_d << 6) | MODE_src_imm);
	LOUT(imm);
}

static inline void
op_movel_Id(int src, int dst)
{
	debug(("movel (%s), %s\n", regname(src), regname(dst)));
	assert_areg(src);
	assert_dreg(dst);
	WOUT(0x2000 | ((dst & 7) << 9) | (MODE_d << 6) | (MODE_ind << 3) | (src & 7));
}

static inline void
op_movel_aI(int src, int dst)
{
	debug(("movel %s, (%s)\n", regname(src), regname(dst)));
	assert_areg(src);
	assert_areg(dst);
	WOUT(0x2000 | ((dst & 7) << 9) | (MODE_ind << 6) | (MODE_a << 3) | (src & 7));
}

static inline void
op_movel_dI(int src, int dst)
{
	debug(("movel %s, (%s)\n", regname(src), regname(dst)));
	assert_dreg(src);
	assert_areg(dst);
	WOUT(0x2000 | ((dst & 7) << 9) | (MODE_ind << 6) | (MODE_d << 3) | (src & 7));
}

static inline void
op_movel_ip(int imm, int dst)
{
	debug(("movel #%d, -(%s)\n", imm, regname(dst)));
	assert_areg(dst);
	WOUT(0x2000 | ((dst & 7) << 9) | (MODE_predec << 6) | MODE_src_imm);
	LOUT(imm);
}

static inline void
op_movel_ap(int src, int dst)
{
	debug(("movel %s, -(%s)\n", regname(src), regname(dst)));
	assert_areg(src);
	assert_areg(dst);
	WOUT(0x2000 | ((dst & 7) << 9) | (MODE_predec << 6) | (MODE_a << 3) | (src & 7));
}

#if defined(JIT3)
static inline void
op_movel_pd(int src, int dst)
{
	debug(("movel +(%s), %s\n", regname(src), regname(dst)));
	assert_areg(src);
	assert_dreg(dst);
	WOUT(0x2000 | ((dst & 7) << 9) | (MODE_d << 6) | (MODE_postinc << 3) | (src & 7));
}

static inline void
op_movel_pa(int src, int dst)
{
	debug(("movel +(%s), %s\n", regname(src), regname(dst)));
	assert_areg(src);
	assert_areg(dst);
	WOUT(0x2000 | ((dst & 7) << 9) | (MODE_a << 6) | (MODE_postinc << 3) | (src & 7));
}
#endif

static inline void
op_movel_dp(int src, int dst)
{
	debug(("movel %s, -(%s)\n", regname(src), regname(dst)));
	assert_dreg(src);
	assert_areg(dst);
	WOUT(0x2000 | ((dst & 7) << 9) | (MODE_predec << 6) | (MODE_d << 3) | (src & 7));
}

static inline void
op_movel_op(int base, int disp, int dst)
{
	debug(("movel %d(%s), -(%s)\n", disp, regname(base), regname(dst)));
	assert_areg(base);
	assert_s16(disp);
	assert_areg(dst);
	WOUT(0x2000 | ((dst & 7) << 9) | (MODE_predec << 6) | (MODE_inddisp << 3) | (base & 7));
	WOUT(disp);
}

static inline void
op_movel_od(int base, int disp, int dst)
{
	debug(("movel %d(%s), %s\n", disp, regname(base), regname(dst)));
	assert_areg(base);
	assert_s16(disp);
	assert_dreg(dst);
	WOUT(0x2000 | ((dst & 7) << 9) | (MODE_d << 6) | (MODE_inddisp << 3) | (base & 7));
	WOUT(disp);
}

static inline void
op_moveal_aa(int src, int dst)
{
	debug(("moveal %s, %s\n", regname(src), regname(dst)));
	assert_areg(src);
	assert_areg(dst);
	WOUT(0x2040 | ((dst & 7) << 9) | (MODE_a << 3) | (src & 7));
}

static inline void
op_moveal_Ia(int src, int dst)
{
	debug(("moveal (%s), %s\n", regname(src), regname(dst)));
	assert_areg(src);
	assert_areg(dst);
	WOUT(0x2040 | ((dst & 7) << 9) | (MODE_ind << 3) | (src & 7));
}

static inline void
op_moveal_oa(int base, int disp, int dst)
{
	debug(("moveal %d(%s), %s\n", disp, regname(base), regname(dst)));
	assert_areg(base);
	assert_s16(disp);
	assert_areg(dst);
	WOUT(0x2040 | ((dst & 7) << 9) | (MODE_inddisp << 3) | (base & 7));
	WOUT(disp);
}

static inline void
op_moveal_ia(int imm, int dst)
{
	debug(("moveal #0x%x, %s\n", imm, regname(dst)));
	assert_areg(dst);
	WOUT(0x2040 | ((dst & 7) << 9) | MODE_src_imm);
	LOUT(imm);
}

#if !defined(HAVE_NO_MOVEM)
static inline void
op_moveml_ro(int mask, int areg, int disp)
{
	debug(("moveml 0x%04x, %d(%s)\n", mask, disp, regname(areg)));
	assert_s16(disp);
	assert_areg(areg);
	WOUT(0x48C0 | (MODE_inddisp << 3) | (areg & 7));
	WOUT(mask);
	WOUT(disp);
}

static inline void
op_moveml_or(int areg, int disp, int mask)
{
	debug(("moveml %d(%s), 0x%04x\n", disp, regname(areg), mask));
	assert_s16(disp);
	assert_areg(areg);
	WOUT(0x4CC0 | (MODE_inddisp << 3) | (areg & 7));
	WOUT(mask);
	WOUT(disp);
}

static inline void
op_moveml_rp(int mask, int areg)
{
	debug(("moveml 0x%04x, -(%s)\n", mask, regname(areg)));
	assert_areg(areg);
	WOUT(0x48C0 | (MODE_predec << 3) | (areg & 7));
	WOUT(mask);
}

static inline void
op_moveml_pr(int areg, int mask)
{
	debug(("moveml +(%s), 0x%04x\n", regname(areg), mask));
	assert_areg(areg);
	WOUT(0x4CC0 | (MODE_postinc << 3) | (areg & 7));
	WOUT(mask);
}
#endif

static inline void
op_moveq_id(int imm, int dst)
{
	debug(("moveq #%d, %s\n", imm, regname(dst)));
	assert_dreg(dst);
	assert_s8(imm);
	WOUT(0x7000 | (dst << 9) | (imm & 0xFF));
}

static inline void
op_mulsl_id(int imm, int dst)
{
	debug(("mulsl #%d, %s\n", imm, regname(dst)));
	assert_dreg(dst);
	WOUT(0x4C00 | MODE_src_imm);
	WOUT(0x0800 | (dst << 12));
	LOUT(imm);
}

static inline void
op_mulsl_dd(int src, int dst)
{
	debug(("mulsl %s, %s\n", regname(src), regname(dst)));
	assert_dreg(src);
	assert_dreg(dst);
	WOUT(0x4C00 | (MODE_d << 3) | src);
	WOUT(0x0800 | (dst << 12));
}

static inline void
op_negl_d(int dst)
{
	debug(("negl %s\n", regname(dst)));
	assert_dreg(dst);
	WOUT(0x4480 | (MODE_d << 3) | dst);
}

static inline void
op_negxl_d(int dst)
{
	debug(("negxl %s\n", regname(dst)));
	assert_dreg(dst);
	WOUT(0x4080 | (MODE_d << 3) | dst);
}

static inline void
op_nop(void)
{
	debug(("nop\n"));
	WOUT(0x4E71);
}

static inline void
op_orl_dd(int src, int dst)
{
	debug(("orl %s, %s\n", regname(src), regname(dst)));