jit-arm.def

基于LWVCL开发的库

{
	int r2 = rreg_int(2);
	int r1 = rreg_int(1);
	int w = wreg_int(0);

	op_lshl(w, r1, r2);

	debug(("lshl_int %d, %d, %d\n", w, r1, r2));
}

/* --------------------------------------------------------------------- */

define_insn(load_byte, loadb_RxR)
{
	int r = rreg_int(2);
	int w = wreg_int(0);

	op_load_sb(w, r);

	debug(("load_byte %d, [%d]\n", w, r));
}

define_insn(load_char, loadc_RxR)
{
	int r = rreg_int(2);
	int w = wreg_int(0);

	op_load_sh(w, r);

	debug(("load_char %d, [%d]\n", w, r));
}

define_insn(load_short, loads_RxR)
{
	int r = rreg_int(2);
	int w = wreg_int(0);

	op_load_sh(w, r);

	debug(("load_short %d, [%d]\n", w, r));
}

define_insn(load_int, load_RxR)
{
	int r = rreg_int(2);
	int w = wreg_int(0);

	op_load(w, r);

	debug(("ld %d, [%d]\n", w, r));
}

define_insn(load_offset_int, load_RRC)
{
	int o = const_int(2);
	int r = rreg_int(1);
	int w = wreg_int(0);

	op_load_offset(w,r,o);

	debug(("ld %d,[%d+%d]\n", w, r, o));
}

define_insn(load_float, fload_RxR)
{
	int r = rreg_int(2);
	int w = wreg_float(0);

	op_fload(w, r);

	debug(("load_float %d, [%d]\n", w, r));
}

define_insn(load_double, floadl_RxR)
{
	int r = rreg_int(2);
	int w = wreg_double(0);

	op_floadl(w, r);

	debug(("load_double %d, [%d]\n", w, r));
}

define_insn(store_byte, storeb_xRR)
{
	int w = rreg_int(2);
	int r = rreg_int(1);

	op_store_b(w, r);
	debug(("store_byte %d, [%d]\n", r, w));
}

define_insn(store_short, stores_xRR)
{
	int w = rreg_int(2);
	int r = rreg_int(1);

	op_store_h(w, r);

	debug(("store_short %d, [%d]\n", r, w));
}

define_insn(store_int, store_xRR)
{
	int r = rreg_int(2);
	int w = rreg_int(1);

	op_store(r, w);

	debug(("store_int %d, [%d]\n", r, w));
}

define_insn(store_offset_int, store_xRRC)
{
	int o = const_int(2);
	int r = rreg_int(1);
	int w = rreg_int(0);

	op_store_offset(r,w,o);

	debug(("st %d,[%d+%d]\n", r, w, o));
}

define_insn(store_float, fstore_RxR)
{
	int r = rreg_float(2);
	int w = rreg_int(1);

	op_fstore(r, w);

	debug(("store_float %d, [%d]\n", r, w));
}

define_insn(store_double, fstorel_RxR)
{
	int r = rreg_double(2);
	int w = rreg_int(1);

	op_fstorel(r, w);

	debug(("store_double %d, [%d]\n", r, w));
}

/* --------------------------------------------------------------------- */

define_insn(cmp_int, cmp_xRR)
{
	int r1 = rreg_int(1);
	int r2 = rreg_int(2);

	op_cmp(r1, r2);

	debug(("cmp_int r%d, r%d\n", r1, r2));
}

define_insn(cmp_int_const, cmp_xRC)
{
	int r = rreg_int(1);
	int o = const_int(2);

	op_cmp_const(r, o);

	debug(("cmp_int_const r%d, #%d\n", r, o));
}

define_insn(cmp_ref, cmpref_xRR)
{
	int r1 = rreg_ref(1);
	int r2 = rreg_ref(2);

	op_cmp(r1, r2);

	debug(("cmp_ref r%d, r%d\n", r1, r2));
}

define_insn(cmp_ref_const, cmpref_xRC)
{
	int r = rreg_ref(1);
	int o = const_int(2);

	op_cmp_const(r, o);

	debug(("cmp_ref_const r%d, #%d\n", r, o));
}


/* --------------------------------------------------------------------- */

define_insn(cvt_int_float, cvtif_RxR)
{
	int r = rreg_int(2); /* CHECKME */
	int w = wreg_float(0);
	op_cvt_i2f(w,r);
	debug(("cvt_int_float %d, %d\n", w, r));
}

define_insn(cvt_int_double, cvtid_RxR)
{
	int r = rreg_int(2);
	int w = wreg_double(0);
	op_cvt_i2d(w,r);
	debug(("cvt_int_double %d, %d\n", w, r));
}

define_insn(cvt_int_double, cvtdi_RxR)
{
	int r = rreg_double(2);
	int w = wreg_int(0);
	op_cvt_f2i(w,r);
	debug(("cvt_double_int %d, %d\n", w, r));
}

define_insn(cvt_float_double, cvtfd_RxR)
{
	int r = rreg_float(2);
	int w = wreg_double(0);
	op_fmovl(w,r);
	debug(("cvt_float_double f%d, f%d\n",w,r));
}

define_insn(cvt_double_float, cvtdf_RxR)
{
	int r = rreg_double(2);
	int w = wreg_float(0);
	op_fmov(w,r);
	debug(("cvt_double_float f%d, f%d\n",w,r));
}

/* --------------------------------------------------------------------- */

define_insn(build_key, set_word_xxC)
{
	jint val = const_int(2);

	LOUT(val);

	debug(("build_key %d", val));
}

define_insn(build_code_ref, set_wordpc_xxC)
{
	label* l = const_label(2);

	l->type |= Llong|Labsolute;
	l->at = CODEPC;
	l->from = CODEPC;
	LOUT(0);

	debug(("build_code_ref (@0x%x from 0x%x)\n", l->at, l->from));
}

/* --------------------------------------------------------------------- */

define_insn(set_label, set_label_xxC)
{
	label* l = const_label(2);

	l->to = CODEPC;

	debug(("set_label (@0x%x to 0x%x)\n", l->at, l->to));
}

define_insn(branch, branch_xCC)
{
	label* l = const_label(1);
	int bt = const_int(2);

	l->type |= Llong26|Lrelative;

	l->at = CODEPC;
	l->from = CODEPC + 8;

	switch (bt) {
	case ba:
		op_branch(CC_AL, 0);
		break;
	case beq:
		op_branch(CC_EQ, 0);
		break;
	case bne:
		op_branch(CC_NE, 0);
		break;
	case blt:
		op_branch(CC_LT, 0);
		break;
	case ble:
		op_branch(CC_LE, 0);
		break;
	case bgt:
		op_branch(CC_GT, 0);
		break;
	case bge:
		op_branch(CC_GE, 0);
		break;
	case bult:
		op_branch(CC_CC, 0);
		break;
	case bugt:
		op_branch(CC_HI, 0);
		break;
	case buge:
		op_branch(CC_CS, 0);
		break;
	default:
		abort();
	}

	debug(("branch type %d at 0x%x from 0x%x\n", bt, l -> at, l -> from));
}

define_insn(call, call_xRC)
{
	int r = rreg_int(1);
	assert(const_int(2) == ba);

	op_mov(LR, PC);
	op_mov(PC, r);

	debug(("call [%d]\n", r));
}

define_insn(branch_indirect, branch_indirect_xRC)
{
	int r = rreg_int(1);
	assert(const_int(2) == ba);
	op_mov(PC, r);
	debug(("branch_indirect [r%d]\n", r));
}

define_insn(push_int, push_xRC)
{
	int a = const_int(2);
	int r;

	/* Tell register allocator we prefer register R0+a 
	 * XXX: This should go in a macro `rreg_int_pref(1, R0+a)'
	 */
	if (a < 4) {
	 	KaffeVM_jitSetIdealReg(R0 + a);
	}
	r = rreg_int(1);
	KaffeVM_jitSetIdealReg(NOREG);	/* reset idealReg */

	if (a < 4) {
		int w = R0 + a;
		clobberRegister(w);
		register_reserve(w);

		if (r != w) {
			op_mov(w, r);

			debug(("push_int via mov %d,%d\n", w, r));
		} 
	}
	else {
		op_push(SP, r);
		debug(("push_int via push SP,r%d\n", r));
	}

}

define_insn(push_float, fpush_xRC)
{
	int r;
	int w;
	int a = const_int(2);


	switch (a) {
	case 0:
	case 1:
	case 2:
	case 3:
		w = R0 + a;
		clobberRegister(w);
		register_reserve(w);
		/*
		 * Push it on to the stack
		 */
		r = rreg_float(1);
		op_fpush(SP, r);
		/*
		 * Now pop it into the register pair
		 */
		op_pop_m(SP, (1 << w));
		debug(("push_float via elaborate mov r(%d) := f%d\n", w, r));
		break;

	default:
		/*
		 * Push it on to the stack
		 */
		r = rreg_float(1);
		op_fpush(SP, r);
		debug(("push_float via SP, f%d\n", r));
		break;
	}
}


define_insn(push_double, fpushl_xRC)
{
	int r;
	int w;
	int a = const_int(2);


	switch (a) {
	case 0:
	case 1:
	case 2:
		w = R0 + a;
		clobberRegister(w);
		register_reserve(w);
		clobberRegister(w+1);
		register_reserve(w+1);
		/*
		 * Push it on to the stack
		 */
		r = rreg_double(1);
		op_fpushl(SP, r);
		/*
		 * Now pop it into the register pair
		 */
		op_pop_m(SP, (1 << w) | (1 << (w+1)));
		debug(("push_double via elaborate mov r(%d,%d) := f%d\n", w, w+1, r));
		break;

	case 3:
		/*
		 * Pass half of the double in R3, half on the stack
		 */
		w = R3;
		clobberRegister(w);
		register_reserve(w);
		r = rreg_double(1);
		op_fpushl(SP, r);

		/* Pop the first word */
		op_pop_m(SP, (1 << w));
		debug(("push_double via partial register, partial stack SP, f%d\n", r));
		break;

	default:
		/*
		 * Push it on to the stack
		 */
		r = rreg_double(1);
		op_fpushl(SP, r);
		debug(("push_double via SP, f%d\n", r));
		break;
	}
}

define_insn(popargs, popargs_xxC)
{
	int o = const_int(2);
	int i;

	/* Reset reserve bit for all register arguments */
	for (i = 0; i < 4 && i < o; i++) {
		register_unreserve(R0 + i);
	}

	/* Don't bother if we have 4 or less arguments to pop */
	if (o > 4) {
		o = (o - 4) * SLOTSIZE;
		assert(__I8const_rangecheck(o >> 2));
		op_add_c(SP, SP, (o >> 2), 30);

		debug(("popargs SP, SP, %d\n", o));
	} else {
		debug(("null popargs with %d args\n", const_int(2)));
	}
}

define_insn(returnarg_int, returnarg_xxR)
{
	int r = rreg_int(2);

	xop_mov(R0, r);

	debug(("returnarg_int R0,%d\n", r));
}

define_insn(returnarg_long, returnargl_xxR)
{
	REGSLOT* r;
	int r1;  
	int r2;

	r = seq_slot(s, 2);
	r1 = _slowSlotRegister(r, Rint, rread);
	r2 = _slowSlotRegister(r+1, Rint, rread);

	debug(("returnarg_long R0,%d,%d\n", r1, r2));

	/* Return long is a bit complicated since part of the source may
	 * be the destination.
	 */ 
	if (R0 != r2) {
		op_mov(R0, r1);
		op_mov(R1, r2);
	}
	else if (R1 != r1) {
		op_mov(R1, r2);
		op_mov(R0, r1);
	}
	else {
		/* Need to swap R0 and R1.  Force R0 into R2 (writing back
		 * R2 if necessary) and then move things about until the
		 * swap is done.
		 */
		forceRegister(r, R2, Rint);
		op_mov(R2, R0);
		op_mov(R0, R1);
		op_mov(R1, R2);
	}
}

define_insn(returnarg_float, freturnarg_xxR)
{
	int r = rreg_float(2);

	xop_fmov(F0, r);

	debug(("returnarg_float R0,%d\n", r));
}

define_insn(returnarg_double, freturnargl_xxR)
{
	int r = rreg_double(2);

	xop_fmovl(F0, r);

	debug(("returnarg_double R0,%d\n", r));
}

define_insn(return_int, return_Rxx)
{
	forceRegister(seq_dst(s), R0, Rint);

	debug(("return_int R0\n"));
}

define_insn(return_long, returnl_Rxx)
{
	forceRegister(seq_dst(s), R0, Rint);
	forceRegister(seq_dst(s)+1, R1, Rint);

	debug(("return_long R0,R1\n"));
}

define_insn(return_float, freturn_Rxx)
{
	forceRegister(seq_dst(s), Reg_F0, Rfloat);

	debug(("return_float F0\n"));
}

define_insn(return_double, freturnl_Rxx)
{
	forceRegister(seq_dst(s), Reg_F0, Rdouble);

	debug(("return_double F0\n"));
}

/* --------------------------------------------------------------------- */