tqm85xx.c

U-BOOT,著名的Bootloader程序

#endif
		return sys_info.freqSystemBus / clkdiv;
	}

	puts("Invalid clock divider value in CFG_LBC_LCRR\n");

	return 0;
}

/*
 * Initialize Local Bus
 */
void local_bus_init (void)
{
	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
	volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
	uint lbc_mhz = get_lbc_clock ()  / 1000000;

#ifdef CONFIG_MPC8548
	uint svr = get_svr ();
	uint lcrr;

	/*
	 * MPC revision < 2.0
	 * According to MPC8548E_Device_Errata Rev. L, Erratum LBIU1:
	 * Modify engineering use only register at address 0xE_0F20.
	 * "1. Read register at offset 0xE_0F20
	 * 2. And value with 0x0000_FFFF
	 * 3. OR result with 0x0000_0004
	 * 4. Write result back to offset 0xE_0F20."
	 *
	 * According to MPC8548E_Device_Errata Rev. L, Erratum LBIU2:
	 * Modify engineering use only register at address 0xE_0F20.
	 * "1. Read register at offset 0xE_0F20
	 * 2. And value with 0xFFFF_FFDF
	 * 3. Write result back to offset 0xE_0F20."
	 *
	 * Since it is the same register, we do the modification in one step.
	 */
	if (SVR_MAJ (svr) < 2) {
		uint dummy = gur->lbiuiplldcr1;
		dummy &= 0x0000FFDF;
		dummy |= 0x00000004;
		gur->lbiuiplldcr1 = dummy;
	}

	lcrr = CFG_LBC_LCRR;

	/*
	 * Local Bus Clock > 83.3 MHz. According to timing
	 * specifications set LCRR[EADC] to 2 delay cycles.
	 */
	if (lbc_mhz > 83) {
		lcrr &= ~LCRR_EADC;
		lcrr |= LCRR_EADC_2;
	}

	/*
	 * According to MPC8548ERMAD Rev. 1.3, 13.3.1.16, 13-30
	 * disable PLL bypass for Local Bus Clock > 83 MHz.
	 */
	if (lbc_mhz >= 66)
		lcrr &= (~LCRR_DBYP);	/* DLL Enabled */

	else
		lcrr |= LCRR_DBYP;	/* DLL Bypass */

	lbc->lcrr = lcrr;
	asm ("sync;isync;msync");

	/*
	 * According to MPC8548ERMAD Rev.1.3 read back LCRR
	 * and terminate with isync
	 */
	lcrr = lbc->lcrr;
	asm ("isync;");

	/* let DLL stabilize */
	udelay (500);

#else /* !CONFIG_MPC8548 */

	/*
	 * Errata LBC11.
	 * Fix Local Bus clock glitch when DLL is enabled.
	 *
	 * If localbus freq is < 66Mhz, DLL bypass mode must be used.
	 * If localbus freq is > 133Mhz, DLL can be safely enabled.
	 * Between 66 and 133, the DLL is enabled with an override workaround.
	 */

	if (lbc_mhz < 66) {
		lbc->lcrr = CFG_LBC_LCRR | LCRR_DBYP;	/* DLL Bypass */
		lbc->ltedr = LTEDR_BMD | LTEDR_PARD | LTEDR_WPD | LTEDR_WARA |
			     LTEDR_RAWA | LTEDR_CSD;	/* Disable all error checking */

	} else if (lbc_mhz >= 133) {
		lbc->lcrr = CFG_LBC_LCRR & (~LCRR_DBYP);	/* DLL Enabled */

	} else {
		/*
		 * On REV1 boards, need to change CLKDIV before enable DLL.
		 * Default CLKDIV is 8, change it to 4 temporarily.
		 */
		uint pvr = get_pvr ();
		uint temp_lbcdll = 0;

		if (pvr == PVR_85xx_REV1) {
			/* FIXME: Justify the high bit here. */
			lbc->lcrr = 0x10000004;
		}

		lbc->lcrr = CFG_LBC_LCRR & (~LCRR_DBYP);	/* DLL Enabled */
		udelay (200);

		/*
		 * Sample LBC DLL ctrl reg, upshift it to set the
		 * override bits.
		 */
		temp_lbcdll = gur->lbcdllcr;
		gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
		asm ("sync;isync;msync");
	}
#endif /* !CONFIG_MPC8548 */

#ifdef	CONFIG_CAN_DRIVER
	/*
	 * According to timing specifications EAD must be
	 * set if Local Bus Clock is > 83 MHz.
	 */
	if (lbc_mhz > 83)
		out_be32 (&lbc->or2, CFG_OR2_CAN | OR_UPM_EAD);
	else
		out_be32 (&lbc->or2, CFG_OR2_CAN);
	out_be32 (&lbc->br2, CFG_BR2_CAN);

	/* LGPL4 is UPWAIT */
	out_be32(&lbc->mcmr, MxMR_DSx_3_CYCL | MxMR_GPL_x4DIS | MxMR_WLFx_3X);

	/* Initialize UPMC for CAN: single read */
	upmc_write (0x00, 0xFFFFED00);
	upmc_write (0x01, 0xCCFFCC00);
	upmc_write (0x02, 0x00FFCF00);
	upmc_write (0x03, 0x00FFCF00);
	upmc_write (0x04, 0x00FFDC00);
	upmc_write (0x05, 0x00FFCF00);
	upmc_write (0x06, 0x00FFED00);
	upmc_write (0x07, 0x3FFFCC07);

	/* Initialize UPMC for CAN: single write */
	upmc_write (0x18, 0xFFFFED00);
	upmc_write (0x19, 0xCCFFEC00);
	upmc_write (0x1A, 0x00FFED80);
	upmc_write (0x1B, 0x00FFED80);
	upmc_write (0x1C, 0x00FFFC00);
	upmc_write (0x1D, 0x0FFFEC00);
	upmc_write (0x1E, 0x0FFFEF00);
	upmc_write (0x1F, 0x3FFFEC05);
#endif /* CONFIG_CAN_DRIVER */
}

/*
 * Initialize PCI Devices, report devices found.
 */
static int first_free_busno;

#if defined(CONFIG_PCI) || defined(CONFIG_PCI1)
static struct pci_controller pci1_hose;
#endif /* CONFIG_PCI || CONFIG_PCI1 */

#ifdef CONFIG_PCIE1
static struct pci_controller pcie1_hose;
#endif /* CONFIG_PCIE1 */

static inline void init_pci1(void)
{
	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
#if defined(CONFIG_PCI) || defined(CONFIG_PCI1)
	uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)CFG_PCI1_ADDR;
	extern void fsl_pci_init(struct pci_controller *hose);
	struct pci_controller *hose = &pci1_hose;

	/* PORDEVSR[15] */
	uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32;
	/* PORDEVSR[14] */
	uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
	/* PORPLLSR[16] */
	uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;

	uint pci_agent = (host_agent == 3) || (host_agent == 4 ) ||
		(host_agent == 6);

	uint pci_speed = CONFIG_SYS_CLK_FREQ;	/* PCI PSPEED in [4:5] */

	if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) {
		printf ("PCI1:  %d bit, %s MHz, %s, %s, %s\n",
			(pci_32) ? 32 : 64,
			(pci_speed == 33333333) ? "33" :
			(pci_speed == 66666666) ? "66" : "unknown",
			pci_clk_sel ? "sync" : "async",
			pci_agent ? "agent" : "host",
			pci_arb ? "arbiter" : "external-arbiter");


		/* inbound */
		pci_set_region (hose->regions + 0,
				CFG_PCI_MEMORY_BUS,
				CFG_PCI_MEMORY_PHYS,
				CFG_PCI_MEMORY_SIZE,
				PCI_REGION_MEM | PCI_REGION_MEMORY);


		/* outbound memory */
		pci_set_region (hose->regions + 1,
				CFG_PCI1_MEM_BASE,
				CFG_PCI1_MEM_PHYS,
				CFG_PCI1_MEM_SIZE,
				PCI_REGION_MEM);

		/* outbound io */
		pci_set_region (hose->regions + 2,
				CFG_PCI1_IO_BASE,
				CFG_PCI1_IO_PHYS,
				CFG_PCI1_IO_SIZE,
				PCI_REGION_IO);

		hose->region_count = 3;

		hose->first_busno = first_free_busno;
		pci_setup_indirect (hose, (int)&pci->cfg_addr,
				    (int)&pci->cfg_data);

		fsl_pci_init (hose);

		printf ("       PCI on bus %02x..%02x\n",
			hose->first_busno, hose->last_busno);

		first_free_busno = hose->last_busno + 1;
#ifdef CONFIG_PCIX_CHECK
		if (!(gur->pordevsr & PORDEVSR_PCI)) {
			ushort reg16 =
				PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ |
				PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
			uint dev = PCI_BDF(hose->first_busno, 0, 0);

			/* PCI-X init */
			if (CONFIG_SYS_CLK_FREQ < 66000000)
				puts ("PCI-X will only work at 66 MHz\n");

			pci_hose_write_config_word (hose, dev, PCIX_COMMAND,
						    reg16);
		}
#endif
	} else {
		puts ("PCI1:  disabled\n");
	}
#else /* !(CONFIG_PCI || CONFIG_PCI1) */
	gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
#endif /* CONFIG_PCI || CONFIG_PCI1) */
}

static inline void init_pcie1(void)
{
	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
#ifdef CONFIG_PCIE1
	uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
	uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)CFG_PCIE1_ADDR;
	extern void fsl_pci_init(struct pci_controller *hose);
	struct pci_controller *hose = &pcie1_hose;
	int pcie_ep =  (host_agent == 0) || (host_agent == 2 ) ||
		(host_agent == 3);

	int pcie_configured  = io_sel >= 1;

	if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){
		printf ("PCIe:  %s, base address %x",
			pcie_ep ? "End point" : "Root complex", (uint)pci);

		if (pci->pme_msg_det) {
			pci->pme_msg_det = 0xffffffff;
			debug (", with errors. Clearing. Now 0x%08x",
			       pci->pme_msg_det);
		}
		puts ("\n");

		/* inbound */
		pci_set_region (hose->regions + 0,
				CFG_PCI_MEMORY_BUS,
				CFG_PCI_MEMORY_PHYS,
				CFG_PCI_MEMORY_SIZE,
				PCI_REGION_MEM | PCI_REGION_MEMORY);

		/* outbound memory */
		pci_set_region (hose->regions + 1,
				CFG_PCIE1_MEM_BASE,
				CFG_PCIE1_MEM_PHYS,
				CFG_PCIE1_MEM_SIZE,
				PCI_REGION_MEM);

		/* outbound io */
		pci_set_region (hose->regions + 2,
				CFG_PCIE1_IO_BASE,
				CFG_PCIE1_IO_PHYS,
				CFG_PCIE1_IO_SIZE,
				PCI_REGION_IO);

		hose->region_count = 3;

		hose->first_busno = first_free_busno;
		pci_setup_indirect(hose, (int)&pci->cfg_addr,
				   (int)&pci->cfg_data);

		fsl_pci_init (hose);
		printf ("       PCIe on bus %02x..%02x\n",
			hose->first_busno, hose->last_busno);

		first_free_busno = hose->last_busno + 1;

	} else {
		printf ("PCIe:  disabled\n");
	}
#else /* !CONFIG_PCIE1 */
	gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
#endif /* CONFIG_PCIE1 */
}

void pci_init_board (void)
{
	init_pci1();
	init_pcie1();
}

#ifdef CONFIG_OF_BOARD_SETUP
void ft_board_setup (void *blob, bd_t *bd)
{
	int node, tmp[2];
	const char *path;

	ft_cpu_setup (blob, bd);

	node = fdt_path_offset (blob, "/aliases");
	tmp[0] = 0;
	if (node >= 0) {
#if defined(CONFIG_PCI) || defined(CONFIG_PCI1)
		path = fdt_getprop (blob, node, "pci0", NULL);
		if (path) {
			tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
			do_fixup_by_path (blob, path, "bus-range", &tmp, 8, 1);
		}
#endif /* CONFIG_PCI || CONFIG_PCI1 */
#ifdef CONFIG_PCIE1
		path = fdt_getprop (blob, node, "pci1", NULL);
		if (path) {
			tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
			do_fixup_by_path (blob, path, "bus-range", &tmp, 8, 1);
		}
#endif /* CONFIG_PCIE1 */
	}
}
#endif /* CONFIG_OF_BOARD_SETUP */

#ifdef CONFIG_BOARD_EARLY_INIT_R
int board_early_init_r (void)
{
#ifdef CONFIG_PS2MULT
	ps2mult_early_init ();
#endif /* CONFIG_PS2MULT */
	return (0);
}
#endif /* CONFIG_BOARD_EARLY_INIT_R */