📄 bf561_cdef.h
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/* DO NOT EDIT THIS FILE * Automatically generated by generate-cdef-headers.xsl * DO NOT EDIT THIS FILE */#ifndef __BFIN_CDEF_ADSP_BF561_proc__#define __BFIN_CDEF_ADSP_BF561_proc__#include "../mach-common/ADSP-EDN-core_cdef.h"#include "../mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h"#define pSRAM_BASE_ADDR ((uint32_t volatile *)SRAM_BASE_ADDR)#define bfin_read_SRAM_BASE_ADDR() bfin_read32(SRAM_BASE_ADDR)#define bfin_write_SRAM_BASE_ADDR(val) bfin_write32(SRAM_BASE_ADDR, val)#define pDMEM_CONTROL ((uint32_t volatile *)DMEM_CONTROL)#define bfin_read_DMEM_CONTROL() bfin_read32(DMEM_CONTROL)#define bfin_write_DMEM_CONTROL(val) bfin_write32(DMEM_CONTROL, val)#define pDCPLB_STATUS ((uint32_t volatile *)DCPLB_STATUS)#define bfin_read_DCPLB_STATUS() bfin_read32(DCPLB_STATUS)#define bfin_write_DCPLB_STATUS(val) bfin_write32(DCPLB_STATUS, val)#define pDCPLB_FAULT_ADDR ((void * volatile *)DCPLB_FAULT_ADDR)#define bfin_read_DCPLB_FAULT_ADDR() bfin_readPTR(DCPLB_FAULT_ADDR)#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val)#define pDCPLB_ADDR0 ((uint32_t volatile *)DCPLB_ADDR0)#define bfin_read_DCPLB_ADDR0() bfin_read32(DCPLB_ADDR0)#define bfin_write_DCPLB_ADDR0(val) bfin_write32(DCPLB_ADDR0, val)#define pDCPLB_ADDR1 ((uint32_t volatile *)DCPLB_ADDR1)#define bfin_read_DCPLB_ADDR1() bfin_read32(DCPLB_ADDR1)#define bfin_write_DCPLB_ADDR1(val) bfin_write32(DCPLB_ADDR1, val)#define pDCPLB_ADDR2 ((uint32_t volatile *)DCPLB_ADDR2)#define bfin_read_DCPLB_ADDR2() bfin_read32(DCPLB_ADDR2)#define bfin_write_DCPLB_ADDR2(val) bfin_write32(DCPLB_ADDR2, val)#define pDCPLB_ADDR3 ((uint32_t volatile *)DCPLB_ADDR3)#define bfin_read_DCPLB_ADDR3() bfin_read32(DCPLB_ADDR3)#define bfin_write_DCPLB_ADDR3(val) bfin_write32(DCPLB_ADDR3, val)#define pDCPLB_ADDR4 ((uint32_t volatile *)DCPLB_ADDR4)#define bfin_read_DCPLB_ADDR4() bfin_read32(DCPLB_ADDR4)#define bfin_write_DCPLB_ADDR4(val) bfin_write32(DCPLB_ADDR4, val)#define pDCPLB_ADDR5 ((uint32_t volatile *)DCPLB_ADDR5)#define bfin_read_DCPLB_ADDR5() bfin_read32(DCPLB_ADDR5)#define bfin_write_DCPLB_ADDR5(val) bfin_write32(DCPLB_ADDR5, val)#define pDCPLB_ADDR6 ((uint32_t volatile *)DCPLB_ADDR6)#define bfin_read_DCPLB_ADDR6() bfin_read32(DCPLB_ADDR6)#define bfin_write_DCPLB_ADDR6(val) bfin_write32(DCPLB_ADDR6, val)#define pDCPLB_ADDR7 ((uint32_t volatile *)DCPLB_ADDR7)#define bfin_read_DCPLB_ADDR7() bfin_read32(DCPLB_ADDR7)#define bfin_write_DCPLB_ADDR7(val) bfin_write32(DCPLB_ADDR7, val)#define pDCPLB_ADDR8 ((uint32_t volatile *)DCPLB_ADDR8)#define bfin_read_DCPLB_ADDR8() bfin_read32(DCPLB_ADDR8)#define bfin_write_DCPLB_ADDR8(val) bfin_write32(DCPLB_ADDR8, val)#define pDCPLB_ADDR9 ((uint32_t volatile *)DCPLB_ADDR9)#define bfin_read_DCPLB_ADDR9() bfin_read32(DCPLB_ADDR9)#define bfin_write_DCPLB_ADDR9(val) bfin_write32(DCPLB_ADDR9, val)#define pDCPLB_ADDR10 ((uint32_t volatile *)DCPLB_ADDR10)#define bfin_read_DCPLB_ADDR10() bfin_read32(DCPLB_ADDR10)#define bfin_write_DCPLB_ADDR10(val) bfin_write32(DCPLB_ADDR10, val)#define pDCPLB_ADDR11 ((uint32_t volatile *)DCPLB_ADDR11)#define bfin_read_DCPLB_ADDR11() bfin_read32(DCPLB_ADDR11)#define bfin_write_DCPLB_ADDR11(val) bfin_write32(DCPLB_ADDR11, val)#define pDCPLB_ADDR12 ((uint32_t volatile *)DCPLB_ADDR12)#define bfin_read_DCPLB_ADDR12() bfin_read32(DCPLB_ADDR12)#define bfin_write_DCPLB_ADDR12(val) bfin_write32(DCPLB_ADDR12, val)#define pDCPLB_ADDR13 ((uint32_t volatile *)DCPLB_ADDR13)#define bfin_read_DCPLB_ADDR13() bfin_read32(DCPLB_ADDR13)#define bfin_write_DCPLB_ADDR13(val) bfin_write32(DCPLB_ADDR13, val)#define pDCPLB_ADDR14 ((uint32_t volatile *)DCPLB_ADDR14)#define bfin_read_DCPLB_ADDR14() bfin_read32(DCPLB_ADDR14)#define bfin_write_DCPLB_ADDR14(val) bfin_write32(DCPLB_ADDR14, val)#define pDCPLB_ADDR15 ((uint32_t volatile *)DCPLB_ADDR15)#define bfin_read_DCPLB_ADDR15() bfin_read32(DCPLB_ADDR15)#define bfin_write_DCPLB_ADDR15(val) bfin_write32(DCPLB_ADDR15, val)#define pDCPLB_DATA0 ((uint32_t volatile *)DCPLB_DATA0)#define bfin_read_DCPLB_DATA0() bfin_read32(DCPLB_DATA0)#define bfin_write_DCPLB_DATA0(val) bfin_write32(DCPLB_DATA0, val)#define pDCPLB_DATA1 ((uint32_t volatile *)DCPLB_DATA1)#define bfin_read_DCPLB_DATA1() bfin_read32(DCPLB_DATA1)#define bfin_write_DCPLB_DATA1(val) bfin_write32(DCPLB_DATA1, val)#define pDCPLB_DATA2 ((uint32_t volatile *)DCPLB_DATA2)#define bfin_read_DCPLB_DATA2() bfin_read32(DCPLB_DATA2)#define bfin_write_DCPLB_DATA2(val) bfin_write32(DCPLB_DATA2, val)#define pDCPLB_DATA3 ((uint32_t volatile *)DCPLB_DATA3)#define bfin_read_DCPLB_DATA3() bfin_read32(DCPLB_DATA3)#define bfin_write_DCPLB_DATA3(val) bfin_write32(DCPLB_DATA3, val)#define pDCPLB_DATA4 ((uint32_t volatile *)DCPLB_DATA4)#define bfin_read_DCPLB_DATA4() bfin_read32(DCPLB_DATA4)#define bfin_write_DCPLB_DATA4(val) bfin_write32(DCPLB_DATA4, val)#define pDCPLB_DATA5 ((uint32_t volatile *)DCPLB_DATA5)#define bfin_read_DCPLB_DATA5() bfin_read32(DCPLB_DATA5)#define bfin_write_DCPLB_DATA5(val) bfin_write32(DCPLB_DATA5, val)#define pDCPLB_DATA6 ((uint32_t volatile *)DCPLB_DATA6)#define bfin_read_DCPLB_DATA6() bfin_read32(DCPLB_DATA6)#define bfin_write_DCPLB_DATA6(val) bfin_write32(DCPLB_DATA6, val)#define pDCPLB_DATA7 ((uint32_t volatile *)DCPLB_DATA7)#define bfin_read_DCPLB_DATA7() bfin_read32(DCPLB_DATA7)#define bfin_write_DCPLB_DATA7(val) bfin_write32(DCPLB_DATA7, val)#define pDCPLB_DATA8 ((uint32_t volatile *)DCPLB_DATA8)#define bfin_read_DCPLB_DATA8() bfin_read32(DCPLB_DATA8)#define bfin_write_DCPLB_DATA8(val) bfin_write32(DCPLB_DATA8, val)#define pDCPLB_DATA9 ((uint32_t volatile *)DCPLB_DATA9)#define bfin_read_DCPLB_DATA9() bfin_read32(DCPLB_DATA9)#define bfin_write_DCPLB_DATA9(val) bfin_write32(DCPLB_DATA9, val)#define pDCPLB_DATA10 ((uint32_t volatile *)DCPLB_DATA10)#define bfin_read_DCPLB_DATA10() bfin_read32(DCPLB_DATA10)#define bfin_write_DCPLB_DATA10(val) bfin_write32(DCPLB_DATA10, val)#define pDCPLB_DATA11 ((uint32_t volatile *)DCPLB_DATA11)#define bfin_read_DCPLB_DATA11() bfin_read32(DCPLB_DATA11)#define bfin_write_DCPLB_DATA11(val) bfin_write32(DCPLB_DATA11, val)#define pDCPLB_DATA12 ((uint32_t volatile *)DCPLB_DATA12)#define bfin_read_DCPLB_DATA12() bfin_read32(DCPLB_DATA12)#define bfin_write_DCPLB_DATA12(val) bfin_write32(DCPLB_DATA12, val)#define pDCPLB_DATA13 ((uint32_t volatile *)DCPLB_DATA13)#define bfin_read_DCPLB_DATA13() bfin_read32(DCPLB_DATA13)#define bfin_write_DCPLB_DATA13(val) bfin_write32(DCPLB_DATA13, val)#define pDCPLB_DATA14 ((uint32_t volatile *)DCPLB_DATA14)#define bfin_read_DCPLB_DATA14() bfin_read32(DCPLB_DATA14)#define bfin_write_DCPLB_DATA14(val) bfin_write32(DCPLB_DATA14, val)#define pDCPLB_DATA15 ((uint32_t volatile *)DCPLB_DATA15)#define bfin_read_DCPLB_DATA15() bfin_read32(DCPLB_DATA15)#define bfin_write_DCPLB_DATA15(val) bfin_write32(DCPLB_DATA15, val)#define pDTEST_COMMAND ((uint32_t volatile *)DTEST_COMMAND)#define bfin_read_DTEST_COMMAND() bfin_read32(DTEST_COMMAND)#define bfin_write_DTEST_COMMAND(val) bfin_write32(DTEST_COMMAND, val)#define pDTEST_DATA0 ((uint32_t volatile *)DTEST_DATA0)#define bfin_read_DTEST_DATA0() bfin_read32(DTEST_DATA0)#define bfin_write_DTEST_DATA0(val) bfin_write32(DTEST_DATA0, val)#define pDTEST_DATA1 ((uint32_t volatile *)DTEST_DATA1)#define bfin_read_DTEST_DATA1() bfin_read32(DTEST_DATA1)#define bfin_write_DTEST_DATA1(val) bfin_write32(DTEST_DATA1, val)#define pIMEM_CONTROL ((uint32_t volatile *)IMEM_CONTROL)#define bfin_read_IMEM_CONTROL() bfin_read32(IMEM_CONTROL)#define bfin_write_IMEM_CONTROL(val) bfin_write32(IMEM_CONTROL, val)#define pICPLB_STATUS ((uint32_t volatile *)ICPLB_STATUS)#define bfin_read_ICPLB_STATUS() bfin_read32(ICPLB_STATUS)#define bfin_write_ICPLB_STATUS(val) bfin_write32(ICPLB_STATUS, val)#define pICPLB_FAULT_ADDR ((uint32_t volatile *)ICPLB_FAULT_ADDR)#define bfin_read_ICPLB_FAULT_ADDR() bfin_read32(ICPLB_FAULT_ADDR)#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_write32(ICPLB_FAULT_ADDR, val)#define pICPLB_ADDR0 ((uint32_t volatile *)ICPLB_ADDR0)#define bfin_read_ICPLB_ADDR0() bfin_read32(ICPLB_ADDR0)#define bfin_write_ICPLB_ADDR0(val) bfin_write32(ICPLB_ADDR0, val)#define pICPLB_ADDR1 ((uint32_t volatile *)ICPLB_ADDR1)#define bfin_read_ICPLB_ADDR1() bfin_read32(ICPLB_ADDR1)#define bfin_write_ICPLB_ADDR1(val) bfin_write32(ICPLB_ADDR1, val)#define pICPLB_ADDR2 ((uint32_t volatile *)ICPLB_ADDR2)#define bfin_read_ICPLB_ADDR2() bfin_read32(ICPLB_ADDR2)#define bfin_write_ICPLB_ADDR2(val) bfin_write32(ICPLB_ADDR2, val)#define pICPLB_ADDR3 ((uint32_t volatile *)ICPLB_ADDR3)#define bfin_read_ICPLB_ADDR3() bfin_read32(ICPLB_ADDR3)#define bfin_write_ICPLB_ADDR3(val) bfin_write32(ICPLB_ADDR3, val)#define pICPLB_ADDR4 ((uint32_t volatile *)ICPLB_ADDR4)#define bfin_read_ICPLB_ADDR4() bfin_read32(ICPLB_ADDR4)#define bfin_write_ICPLB_ADDR4(val) bfin_write32(ICPLB_ADDR4, val)#define pICPLB_ADDR5 ((uint32_t volatile *)ICPLB_ADDR5)#define bfin_read_ICPLB_ADDR5() bfin_read32(ICPLB_ADDR5)#define bfin_write_ICPLB_ADDR5(val) bfin_write32(ICPLB_ADDR5, val)#define pICPLB_ADDR6 ((uint32_t volatile *)ICPLB_ADDR6)⌨️ 快捷键说明
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