adsp-edn-bf542-extended_cdef.h

U-BOOT,著名的Bootloader程序

/* DO NOT EDIT THIS FILE
 * Automatically generated by generate-cdef-headers.xsl
 * DO NOT EDIT THIS FILE
 */

#ifndef __BFIN_CDEF_ADSP_EDN_BF542_extended__
#define __BFIN_CDEF_ADSP_EDN_BF542_extended__

#define pSIC_IMASK0                    ((uint32_t volatile *)SIC_IMASK0) /* System Interrupt Mask Register 0 */
#define bfin_read_SIC_IMASK0()         bfin_read32(SIC_IMASK0)
#define bfin_write_SIC_IMASK0(val)     bfin_write32(SIC_IMASK0, val)
#define pSIC_IMASK1                    ((uint32_t volatile *)SIC_IMASK1) /* System Interrupt Mask Register 1 */
#define bfin_read_SIC_IMASK1()         bfin_read32(SIC_IMASK1)
#define bfin_write_SIC_IMASK1(val)     bfin_write32(SIC_IMASK1, val)
#define pSIC_IMASK2                    ((uint32_t volatile *)SIC_IMASK2) /* System Interrupt Mask Register 2 */
#define bfin_read_SIC_IMASK2()         bfin_read32(SIC_IMASK2)
#define bfin_write_SIC_IMASK2(val)     bfin_write32(SIC_IMASK2, val)
#define pSIC_ISR0                      ((uint32_t volatile *)SIC_ISR0) /* System Interrupt Status Register 0 */
#define bfin_read_SIC_ISR0()           bfin_read32(SIC_ISR0)
#define bfin_write_SIC_ISR0(val)       bfin_write32(SIC_ISR0, val)
#define pSIC_ISR1                      ((uint32_t volatile *)SIC_ISR1) /* System Interrupt Status Register 1 */
#define bfin_read_SIC_ISR1()           bfin_read32(SIC_ISR1)
#define bfin_write_SIC_ISR1(val)       bfin_write32(SIC_ISR1, val)
#define pSIC_ISR2                      ((uint32_t volatile *)SIC_ISR2) /* System Interrupt Status Register 2 */
#define bfin_read_SIC_ISR2()           bfin_read32(SIC_ISR2)
#define bfin_write_SIC_ISR2(val)       bfin_write32(SIC_ISR2, val)
#define pSIC_IWR0                      ((uint32_t volatile *)SIC_IWR0) /* System Interrupt Wakeup Register 0 */
#define bfin_read_SIC_IWR0()           bfin_read32(SIC_IWR0)
#define bfin_write_SIC_IWR0(val)       bfin_write32(SIC_IWR0, val)
#define pSIC_IWR1                      ((uint32_t volatile *)SIC_IWR1) /* System Interrupt Wakeup Register 1 */
#define bfin_read_SIC_IWR1()           bfin_read32(SIC_IWR1)
#define bfin_write_SIC_IWR1(val)       bfin_write32(SIC_IWR1, val)
#define pSIC_IWR2                      ((uint32_t volatile *)SIC_IWR2) /* System Interrupt Wakeup Register 2 */
#define bfin_read_SIC_IWR2()           bfin_read32(SIC_IWR2)
#define bfin_write_SIC_IWR2(val)       bfin_write32(SIC_IWR2, val)
#define pSIC_IAR0                      ((uint32_t volatile *)SIC_IAR0) /* System Interrupt Assignment Register 0 */
#define bfin_read_SIC_IAR0()           bfin_read32(SIC_IAR0)
#define bfin_write_SIC_IAR0(val)       bfin_write32(SIC_IAR0, val)
#define pSIC_IAR1                      ((uint32_t volatile *)SIC_IAR1) /* System Interrupt Assignment Register 1 */
#define bfin_read_SIC_IAR1()           bfin_read32(SIC_IAR1)
#define bfin_write_SIC_IAR1(val)       bfin_write32(SIC_IAR1, val)
#define pSIC_IAR2                      ((uint32_t volatile *)SIC_IAR2) /* System Interrupt Assignment Register 2 */
#define bfin_read_SIC_IAR2()           bfin_read32(SIC_IAR2)
#define bfin_write_SIC_IAR2(val)       bfin_write32(SIC_IAR2, val)
#define pSIC_IAR3                      ((uint32_t volatile *)SIC_IAR3) /* System Interrupt Assignment Register 3 */
#define bfin_read_SIC_IAR3()           bfin_read32(SIC_IAR3)
#define bfin_write_SIC_IAR3(val)       bfin_write32(SIC_IAR3, val)
#define pSIC_IAR4                      ((uint32_t volatile *)SIC_IAR4) /* System Interrupt Assignment Register 4 */
#define bfin_read_SIC_IAR4()           bfin_read32(SIC_IAR4)
#define bfin_write_SIC_IAR4(val)       bfin_write32(SIC_IAR4, val)
#define pSIC_IAR5                      ((uint32_t volatile *)SIC_IAR5) /* System Interrupt Assignment Register 5 */
#define bfin_read_SIC_IAR5()           bfin_read32(SIC_IAR5)
#define bfin_write_SIC_IAR5(val)       bfin_write32(SIC_IAR5, val)
#define pSIC_IAR6                      ((uint32_t volatile *)SIC_IAR6) /* System Interrupt Assignment Register 6 */
#define bfin_read_SIC_IAR6()           bfin_read32(SIC_IAR6)
#define bfin_write_SIC_IAR6(val)       bfin_write32(SIC_IAR6, val)
#define pSIC_IAR7                      ((uint32_t volatile *)SIC_IAR7) /* System Interrupt Assignment Register 7 */
#define bfin_read_SIC_IAR7()           bfin_read32(SIC_IAR7)
#define bfin_write_SIC_IAR7(val)       bfin_write32(SIC_IAR7, val)
#define pSIC_IAR8                      ((uint32_t volatile *)SIC_IAR8) /* System Interrupt Assignment Register 8 */
#define bfin_read_SIC_IAR8()           bfin_read32(SIC_IAR8)
#define bfin_write_SIC_IAR8(val)       bfin_write32(SIC_IAR8, val)
#define pSIC_IAR9                      ((uint32_t volatile *)SIC_IAR9) /* System Interrupt Assignment Register 9 */
#define bfin_read_SIC_IAR9()           bfin_read32(SIC_IAR9)
#define bfin_write_SIC_IAR9(val)       bfin_write32(SIC_IAR9, val)
#define pSIC_IAR10                     ((uint32_t volatile *)SIC_IAR10) /* System Interrupt Assignment Register 10 */
#define bfin_read_SIC_IAR10()          bfin_read32(SIC_IAR10)
#define bfin_write_SIC_IAR10(val)      bfin_write32(SIC_IAR10, val)
#define pSIC_IAR11                     ((uint32_t volatile *)SIC_IAR11) /* System Interrupt Assignment Register 11 */
#define bfin_read_SIC_IAR11()          bfin_read32(SIC_IAR11)
#define bfin_write_SIC_IAR11(val)      bfin_write32(SIC_IAR11, val)
#define pDMAC0_TCPER                   ((uint16_t volatile *)DMAC0_TCPER) /* DMA Controller 0 Traffic Control Periods Register */
#define bfin_read_DMAC0_TCPER()        bfin_read16(DMAC0_TCPER)
#define bfin_write_DMAC0_TCPER(val)    bfin_write16(DMAC0_TCPER, val)
#define pDMAC0_TCCNT                   ((uint16_t volatile *)DMAC0_TCCNT) /* DMA Controller 0 Current Counts Register */
#define bfin_read_DMAC0_TCCNT()        bfin_read16(DMAC0_TCCNT)
#define bfin_write_DMAC0_TCCNT(val)    bfin_write16(DMAC0_TCCNT, val)
#define pDMAC1_TCPER                   ((uint16_t volatile *)DMAC1_TCPER) /* DMA Controller 1 Traffic Control Periods Register */
#define bfin_read_DMAC1_TCPER()        bfin_read16(DMAC1_TCPER)
#define bfin_write_DMAC1_TCPER(val)    bfin_write16(DMAC1_TCPER, val)
#define pDMAC1_TCCNT                   ((uint16_t volatile *)DMAC1_TCCNT) /* DMA Controller 1 Current Counts Register */
#define bfin_read_DMAC1_TCCNT()        bfin_read16(DMAC1_TCCNT)
#define bfin_write_DMAC1_TCCNT(val)    bfin_write16(DMAC1_TCCNT, val)
#define pDMAC1_PERIMUX                 ((uint16_t volatile *)DMAC1_PERIMUX) /* DMA Controller 1 Peripheral Multiplexer Register */
#define bfin_read_DMAC1_PERIMUX()      bfin_read16(DMAC1_PERIMUX)
#define bfin_write_DMAC1_PERIMUX(val)  bfin_write16(DMAC1_PERIMUX, val)
#define pDMA0_NEXT_DESC_PTR            ((void * volatile *)DMA0_NEXT_DESC_PTR) /* DMA Channel 0 Next Descriptor Pointer Register */
#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_readPTR(DMA0_NEXT_DESC_PTR)
#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_writePTR(DMA0_NEXT_DESC_PTR, val)
#define pDMA0_START_ADDR               ((void * volatile *)DMA0_START_ADDR) /* DMA Channel 0 Start Address Register */
#define bfin_read_DMA0_START_ADDR()    bfin_readPTR(DMA0_START_ADDR)
#define bfin_write_DMA0_START_ADDR(val) bfin_writePTR(DMA0_START_ADDR, val)
#define pDMA0_CONFIG                   ((uint16_t volatile *)DMA0_CONFIG) /* DMA Channel 0 Configuration Register */
#define bfin_read_DMA0_CONFIG()        bfin_read16(DMA0_CONFIG)
#define bfin_write_DMA0_CONFIG(val)    bfin_write16(DMA0_CONFIG, val)
#define pDMA0_X_COUNT                  ((uint16_t volatile *)DMA0_X_COUNT) /* DMA Channel 0 X Count Register */
#define bfin_read_DMA0_X_COUNT()       bfin_read16(DMA0_X_COUNT)
#define bfin_write_DMA0_X_COUNT(val)   bfin_write16(DMA0_X_COUNT, val)
#define pDMA0_X_MODIFY                 ((uint16_t volatile *)DMA0_X_MODIFY) /* DMA Channel 0 X Modify Register */
#define bfin_read_DMA0_X_MODIFY()      bfin_read16(DMA0_X_MODIFY)
#define bfin_write_DMA0_X_MODIFY(val)  bfin_write16(DMA0_X_MODIFY, val)
#define pDMA0_Y_COUNT                  ((uint16_t volatile *)DMA0_Y_COUNT) /* DMA Channel 0 Y Count Register */
#define bfin_read_DMA0_Y_COUNT()       bfin_read16(DMA0_Y_COUNT)
#define bfin_write_DMA0_Y_COUNT(val)   bfin_write16(DMA0_Y_COUNT, val)
#define pDMA0_Y_MODIFY                 ((uint16_t volatile *)DMA0_Y_MODIFY) /* DMA Channel 0 Y Modify Register */
#define bfin_read_DMA0_Y_MODIFY()      bfin_read16(DMA0_Y_MODIFY)
#define bfin_write_DMA0_Y_MODIFY(val)  bfin_write16(DMA0_Y_MODIFY, val)
#define pDMA0_CURR_DESC_PTR            ((void * volatile *)DMA0_CURR_DESC_PTR) /* DMA Channel 0 Current Descriptor Pointer Register */
#define bfin_read_DMA0_CURR_DESC_PTR() bfin_readPTR(DMA0_CURR_DESC_PTR)
#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_writePTR(DMA0_CURR_DESC_PTR, val)
#define pDMA0_CURR_ADDR                ((void * volatile *)DMA0_CURR_ADDR) /* DMA Channel 0 Current Address Register */
#define bfin_read_DMA0_CURR_ADDR()     bfin_readPTR(DMA0_CURR_ADDR)
#define bfin_write_DMA0_CURR_ADDR(val) bfin_writePTR(DMA0_CURR_ADDR, val)
#define pDMA0_IRQ_STATUS               ((uint16_t volatile *)DMA0_IRQ_STATUS) /* DMA Channel 0 Interrupt/Status Register */
#define bfin_read_DMA0_IRQ_STATUS()    bfin_read16(DMA0_IRQ_STATUS)
#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val)
#define pDMA0_PERIPHERAL_MAP           ((uint16_t volatile *)DMA0_PERIPHERAL_MAP) /* DMA Channel 0 Peripheral Map Register */
#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val)
#define pDMA0_CURR_X_COUNT             ((uint16_t volatile *)DMA0_CURR_X_COUNT) /* DMA Channel 0 Current X Count Register */
#define bfin_read_DMA0_CURR_X_COUNT()  bfin_read16(DMA0_CURR_X_COUNT)
#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val)
#define pDMA0_CURR_Y_COUNT             ((uint16_t volatile *)DMA0_CURR_Y_COUNT) /* DMA Channel 0 Current Y Count Register */
#define bfin_read_DMA0_CURR_Y_COUNT()  bfin_read16(DMA0_CURR_Y_COUNT)
#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val)
#define pDMA1_NEXT_DESC_PTR            ((void * volatile *)DMA1_NEXT_DESC_PTR) /* DMA Channel 1 Next Descriptor Pointer Register */
#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_readPTR(DMA1_NEXT_DESC_PTR)
#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_NEXT_DESC_PTR, val)
#define pDMA1_START_ADDR               ((void * volatile *)DMA1_START_ADDR) /* DMA Channel 1 Start Address Register */
#define bfin_read_DMA1_START_ADDR()    bfin_readPTR(DMA1_START_ADDR)
#define bfin_write_DMA1_START_ADDR(val) bfin_writePTR(DMA1_START_ADDR, val)
#define pDMA1_CONFIG                   ((uint16_t volatile *)DMA1_CONFIG) /* DMA Channel 1 Configuration Register */
#define bfin_read_DMA1_CONFIG()        bfin_read16(DMA1_CONFIG)
#define bfin_write_DMA1_CONFIG(val)    bfin_write16(DMA1_CONFIG, val)
#define pDMA1_X_COUNT                  ((uint16_t volatile *)DMA1_X_COUNT) /* DMA Channel 1 X Count Register */
#define bfin_read_DMA1_X_COUNT()       bfin_read16(DMA1_X_COUNT)
#define bfin_write_DMA1_X_COUNT(val)   bfin_write16(DMA1_X_COUNT, val)
#define pDMA1_X_MODIFY                 ((uint16_t volatile *)DMA1_X_MODIFY) /* DMA Channel 1 X Modify Register */
#define bfin_read_DMA1_X_MODIFY()      bfin_read16(DMA1_X_MODIFY)
#define bfin_write_DMA1_X_MODIFY(val)  bfin_write16(DMA1_X_MODIFY, val)
#define pDMA1_Y_COUNT                  ((uint16_t volatile *)DMA1_Y_COUNT) /* DMA Channel 1 Y Count Register */
#define bfin_read_DMA1_Y_COUNT()       bfin_read16(DMA1_Y_COUNT)
#define bfin_write_DMA1_Y_COUNT(val)   bfin_write16(DMA1_Y_COUNT, val)
#define pDMA1_Y_MODIFY                 ((uint16_t volatile *)DMA1_Y_MODIFY) /* DMA Channel 1 Y Modify Register */
#define bfin_read_DMA1_Y_MODIFY()      bfin_read16(DMA1_Y_MODIFY)
#define bfin_write_DMA1_Y_MODIFY(val)  bfin_write16(DMA1_Y_MODIFY, val)
#define pDMA1_CURR_DESC_PTR            ((void * volatile *)DMA1_CURR_DESC_PTR) /* DMA Channel 1 Current Descriptor Pointer Register */
#define bfin_read_DMA1_CURR_DESC_PTR() bfin_readPTR(DMA1_CURR_DESC_PTR)
#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_CURR_DESC_PTR, val)
#define pDMA1_CURR_ADDR                ((void * volatile *)DMA1_CURR_ADDR) /* DMA Channel 1 Current Address Register */