adsp-edn-bf542-extended_def.h

U-BOOT,著名的Bootloader程序

#define PORTH_DIR_SET                  0xFFC015B0 /* GPIO Direction Set Register */
#define PORTH_DIR_CLEAR                0xFFC015B4 /* GPIO Direction Clear Register */
#define PORTH_INEN                     0xFFC015B8 /* GPIO Input Enable Register */
#define PORTH_MUX                      0xFFC015BC /* Multiplexer Control Register */
#define PORTI_FER                      0xFFC015C0 /* Function Enable Register */
#define PORTI                          0xFFC015C4 /* GPIO Data Register */
#define PORTI_SET                      0xFFC015C8 /* GPIO Data Set Register */
#define PORTI_CLEAR                    0xFFC015CC /* GPIO Data Clear Register */
#define PORTI_DIR_SET                  0xFFC015D0 /* GPIO Direction Set Register */
#define PORTI_DIR_CLEAR                0xFFC015D4 /* GPIO Direction Clear Register */
#define PORTI_INEN                     0xFFC015D8 /* GPIO Input Enable Register */
#define PORTI_MUX                      0xFFC015DC /* Multiplexer Control Register */
#define PORTJ_FER                      0xFFC015E0 /* Function Enable Register */
#define PORTJ                          0xFFC015E4 /* GPIO Data Register */
#define PORTJ_SET                      0xFFC015E8 /* GPIO Data Set Register */
#define PORTJ_CLEAR                    0xFFC015EC /* GPIO Data Clear Register */
#define PORTJ_DIR_SET                  0xFFC015F0 /* GPIO Direction Set Register */
#define PORTJ_DIR_CLEAR                0xFFC015F4 /* GPIO Direction Clear Register */
#define PORTJ_INEN                     0xFFC015F8 /* GPIO Input Enable Register */
#define PORTJ_MUX                      0xFFC015FC /* Multiplexer Control Register */
#define PINT0_MASK_SET                 0xFFC01400 /* Pin Interrupt 0 Mask Set Register */
#define PINT0_MASK_CLEAR               0xFFC01404 /* Pin Interrupt 0 Mask Clear Register */
#define PINT0_IRQ                      0xFFC01408 /* Pin Interrupt 0 Interrupt Request Register */
#define PINT0_ASSIGN                   0xFFC0140C /* Pin Interrupt 0 Port Assign Register */
#define PINT0_EDGE_SET                 0xFFC01410 /* Pin Interrupt 0 Edge-sensitivity Set Register */
#define PINT0_EDGE_CLEAR               0xFFC01414 /* Pin Interrupt 0 Edge-sensitivity Clear Register */
#define PINT0_INVERT_SET               0xFFC01418 /* Pin Interrupt 0 Inversion Set Register */
#define PINT0_INVERT_CLEAR             0xFFC0141C /* Pin Interrupt 0 Inversion Clear Register */
#define PINT0_PINSTATE                 0xFFC01420 /* Pin Interrupt 0 Pin Status Register */
#define PINT0_LATCH                    0xFFC01424 /* Pin Interrupt 0 Latch Register */
#define PINT1_MASK_SET                 0xFFC01430 /* Pin Interrupt 1 Mask Set Register */
#define PINT1_MASK_CLEAR               0xFFC01434 /* Pin Interrupt 1 Mask Clear Register */
#define PINT1_IRQ                      0xFFC01438 /* Pin Interrupt 1 Interrupt Request Register */
#define PINT1_ASSIGN                   0xFFC0143C /* Pin Interrupt 1 Port Assign Register */
#define PINT1_EDGE_SET                 0xFFC01440 /* Pin Interrupt 1 Edge-sensitivity Set Register */
#define PINT1_EDGE_CLEAR               0xFFC01444 /* Pin Interrupt 1 Edge-sensitivity Clear Register */
#define PINT1_INVERT_SET               0xFFC01448 /* Pin Interrupt 1 Inversion Set Register */
#define PINT1_INVERT_CLEAR             0xFFC0144C /* Pin Interrupt 1 Inversion Clear Register */
#define PINT1_PINSTATE                 0xFFC01450 /* Pin Interrupt 1 Pin Status Register */
#define PINT1_LATCH                    0xFFC01454 /* Pin Interrupt 1 Latch Register */
#define PINT2_MASK_SET                 0xFFC01460 /* Pin Interrupt 2 Mask Set Register */
#define PINT2_MASK_CLEAR               0xFFC01464 /* Pin Interrupt 2 Mask Clear Register */
#define PINT2_IRQ                      0xFFC01468 /* Pin Interrupt 2 Interrupt Request Register */
#define PINT2_ASSIGN                   0xFFC0146C /* Pin Interrupt 2 Port Assign Register */
#define PINT2_EDGE_SET                 0xFFC01470 /* Pin Interrupt 2 Edge-sensitivity Set Register */
#define PINT2_EDGE_CLEAR               0xFFC01474 /* Pin Interrupt 2 Edge-sensitivity Clear Register */
#define PINT2_INVERT_SET               0xFFC01478 /* Pin Interrupt 2 Inversion Set Register */
#define PINT2_INVERT_CLEAR             0xFFC0147C /* Pin Interrupt 2 Inversion Clear Register */
#define PINT2_PINSTATE                 0xFFC01480 /* Pin Interrupt 2 Pin Status Register */
#define PINT2_LATCH                    0xFFC01484 /* Pin Interrupt 2 Latch Register */
#define PINT3_MASK_SET                 0xFFC01490 /* Pin Interrupt 3 Mask Set Register */
#define PINT3_MASK_CLEAR               0xFFC01494 /* Pin Interrupt 3 Mask Clear Register */
#define PINT3_IRQ                      0xFFC01498 /* Pin Interrupt 3 Interrupt Request Register */
#define PINT3_ASSIGN                   0xFFC0149C /* Pin Interrupt 3 Port Assign Register */
#define PINT3_EDGE_SET                 0xFFC014A0 /* Pin Interrupt 3 Edge-sensitivity Set Register */
#define PINT3_EDGE_CLEAR               0xFFC014A4 /* Pin Interrupt 3 Edge-sensitivity Clear Register */
#define PINT3_INVERT_SET               0xFFC014A8 /* Pin Interrupt 3 Inversion Set Register */
#define PINT3_INVERT_CLEAR             0xFFC014AC /* Pin Interrupt 3 Inversion Clear Register */
#define PINT3_PINSTATE                 0xFFC014B0 /* Pin Interrupt 3 Pin Status Register */
#define PINT3_LATCH                    0xFFC014B4 /* Pin Interrupt 3 Latch Register */
#define TIMER0_CONFIG                  0xFFC01600 /* Timer 0 Configuration Register */
#define TIMER0_COUNTER                 0xFFC01604 /* Timer 0 Counter Register */
#define TIMER0_PERIOD                  0xFFC01608 /* Timer 0 Period Register */
#define TIMER0_WIDTH                   0xFFC0160C /* Timer 0 Width Register */
#define TIMER1_CONFIG                  0xFFC01610 /* Timer 1 Configuration Register */
#define TIMER1_COUNTER                 0xFFC01614 /* Timer 1 Counter Register */
#define TIMER1_PERIOD                  0xFFC01618 /* Timer 1 Period Register */
#define TIMER1_WIDTH                   0xFFC0161C /* Timer 1 Width Register */
#define TIMER2_CONFIG                  0xFFC01620 /* Timer 2 Configuration Register */
#define TIMER2_COUNTER                 0xFFC01624 /* Timer 2 Counter Register */
#define TIMER2_PERIOD                  0xFFC01628 /* Timer 2 Period Register */
#define TIMER2_WIDTH                   0xFFC0162C /* Timer 2 Width Register */
#define TIMER3_CONFIG                  0xFFC01630 /* Timer 3 Configuration Register */
#define TIMER3_COUNTER                 0xFFC01634 /* Timer 3 Counter Register */
#define TIMER3_PERIOD                  0xFFC01638 /* Timer 3 Period Register */
#define TIMER3_WIDTH                   0xFFC0163C /* Timer 3 Width Register */
#define TIMER4_CONFIG                  0xFFC01640 /* Timer 4 Configuration Register */
#define TIMER4_COUNTER                 0xFFC01644 /* Timer 4 Counter Register */
#define TIMER4_PERIOD                  0xFFC01648 /* Timer 4 Period Register */
#define TIMER4_WIDTH                   0xFFC0164C /* Timer 4 Width Register */
#define TIMER5_CONFIG                  0xFFC01650 /* Timer 5 Configuration Register */
#define TIMER5_COUNTER                 0xFFC01654 /* Timer 5 Counter Register */
#define TIMER5_PERIOD                  0xFFC01658 /* Timer 5 Period Register */
#define TIMER5_WIDTH                   0xFFC0165C /* Timer 5 Width Register */
#define TIMER6_CONFIG                  0xFFC01660 /* Timer 6 Configuration Register */
#define TIMER6_COUNTER                 0xFFC01664 /* Timer 6 Counter Register */
#define TIMER6_PERIOD                  0xFFC01668 /* Timer 6 Period Register */
#define TIMER6_WIDTH                   0xFFC0166C /* Timer 6 Width Register */
#define TIMER7_CONFIG                  0xFFC01670 /* Timer 7 Configuration Register */
#define TIMER7_COUNTER                 0xFFC01674 /* Timer 7 Counter Register */
#define TIMER7_PERIOD                  0xFFC01678 /* Timer 7 Period Register */
#define TIMER7_WIDTH                   0xFFC0167C /* Timer 7 Width Register */
#define TIMER_ENABLE0                  0xFFC01680 /* Timer Group of 8 Enable Register */
#define TIMER_DISABLE0                 0xFFC01684 /* Timer Group of 8 Disable Register */
#define TIMER_STATUS0                  0xFFC01688 /* Timer Group of 8 Status Register */
#define TCNTL                          0xFFE03000 /* Core Timer Control Register */
#define TCOUNT                         0xFFE0300C /* Core Timer Count Register */
#define TPERIOD                        0xFFE03004 /* Core Timer Period Register */
#define TSCALE                         0xFFE03008 /* Core Timer Scale Register */
#define WDOG_CTL                       0xFFC00200 /* Watchdog Control Register */
#define WDOG_CNT                       0xFFC00204 /* Watchdog Count Register */
#define WDOG_STAT                      0xFFC00208 /* Watchdog Status Register */
#define CNT_CONFIG                     0xFFC04200 /* Configuration Register */
#define CNT_IMASK                      0xFFC04204 /* Interrupt Mask Register */
#define CNT_STATUS                     0xFFC04208 /* Status Register  */
#define CNT_COMMAND                    0xFFC0420C /* Command Register */
#define CNT_DEBOUNCE                   0xFFC04210 /* Debounce Register */
#define CNT_COUNTER                    0xFFC04214 /* Counter Register */
#define CNT_MAX                        0xFFC04218 /* Maximal Count Register */
#define CNT_MIN                        0xFFC0421C /* Minimal Count Register */
#define RTC_STAT                       0xFFC00300 /* RTC Status Register */
#define RTC_ICTL                       0xFFC00304 /* RTC Interrupt Control Register */
#define RTC_ISTAT                      0xFFC00308 /* RTC Interrupt Status Register */
#define RTC_SWCNT                      0xFFC0030C /* RTC Stopwatch Count Register */
#define RTC_ALARM                      0xFFC00310 /* RTC Alarm Register */
#define RTC_PREN                       0xFFC00314 /* RTC Prescaler Enable Register */
#define OTP_CONTROL                    0xFFC04300 /* OTP/Fuse Control Register */
#define OTP_BEN                        0xFFC04304 /* OTP/Fuse Byte Enable */
#define OTP_STATUS                     0xFFC04308 /* OTP/Fuse Status */
#define OTP_TIMING                     0xFFC0430C /* OTP/Fuse Access Timing */
#define SECURE_SYSSWT                  0xFFC04320 /* Secure System Switches */
#define SECURE_CONTROL                 0xFFC04324 /* Secure Control */
#define SECURE_STATUS                  0xFFC04328 /* Secure Status */
#define OTP_DATA0                      0xFFC04380 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
#define OTP_DATA1                      0xFFC04384 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
#define OTP_DATA2                      0xFFC04388 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
#define OTP_DATA3                      0xFFC0438C /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
#define PLL_CTL                        0xFFC00000 /* PLL Control Register */
#define PLL_DIV                        0xFFC00004 /* PLL Divisor Register */
#define VR_CTL                         0xFFC00008 /* Voltage Regulator Control Register */
#define PLL_STAT                       0xFFC0000C /* PLL Status Register */
#define PLL_LOCKCNT                    0xFFC00010 /* PLL Lock Count Register */
#define KPAD_CTL                       0xFFC04100 /* Controls keypad module enable and disable */
#define KPAD_PRESCALE                  0xFFC04104 /* Establish a time base for programing the KPAD_MSEL register */
#define KPAD_MSEL                      0xFFC04108 /* Selects delay parameters for keypad interface sensitivity */
#define KPAD_ROWCOL                    0xFFC0410C /* Captures the row and column output values of the keys pressed */
#define KPAD_STAT                      0xFFC04110 /* Holds and clears the status of the keypad interface interrupt */
#define KPAD_SOFTEVAL                  0xFFC04114 /* Lets software force keypad interface to check for keys being pressed */
#define SDH_PWR_CTL                    0xFFC03900 /* SDH Power Control