prev_cmp_myled.tan.qmsg

EP1C3144的点灯基本程序

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register counter\[10\] register counter\[7\] 151.17 MHz 6.615 ns Internal " "Info: Clock \"clk\" has Internal fmax of 151.17 MHz between source register \"counter\[10\]\" and destination register \"counter\[7\]\" (period= 6.615 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.354 ns + Longest register register " "Info: + Longest register to register delay is 6.354 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns counter\[10\] 1 REG LC_X20_Y8_N2 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X20_Y8_N2; Fanout = 7; REG Node = 'counter\[10\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { counter[10] } "NODE_NAME" } } { "myled.vhd" "" { Text "D:/STUDY/qt/myled/myled.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.235 ns) + CELL(0.292 ns) 1.527 ns LessThan5~500 2 COMB LC_X21_Y8_N3 1 " "Info: 2: + IC(1.235 ns) + CELL(0.292 ns) = 1.527 ns; Loc. = LC_X21_Y8_N3; Fanout = 1; COMB Node = 'LessThan5~500'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.527 ns" { counter[10] LessThan5~500 } "NODE_NAME" } } { "myled.vhd" "" { Text "D:/STUDY/qt/myled/myled.vhd" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.114 ns) 1.823 ns LessThan5~501 3 COMB LC_X21_Y8_N4 1 " "Info: 3: + IC(0.182 ns) + CELL(0.114 ns) = 1.823 ns; Loc. = LC_X21_Y8_N4; Fanout = 1; COMB Node = 'LessThan5~501'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.296 ns" { LessThan5~500 LessThan5~501 } "NODE_NAME" } } { "myled.vhd" "" { Text "D:/STUDY/qt/myled/myled.vhd" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.340 ns) + CELL(0.114 ns) 2.277 ns LessThan5~502 4 COMB LC_X21_Y8_N5 1 " "Info: 4: + IC(0.340 ns) + CELL(0.114 ns) = 2.277 ns; Loc. = LC_X21_Y8_N5; Fanout = 1; COMB Node = 'LessThan5~502'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.454 ns" { LessThan5~501 LessThan5~502 } "NODE_NAME" } } { "myled.vhd" "" { Text "D:/STUDY/qt/myled/myled.vhd" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.219 ns) + CELL(0.114 ns) 3.610 ns LessThan5~504 5 COMB LC_X20_Y7_N8 1 " "Info: 5: + IC(1.219 ns) + CELL(0.114 ns) = 3.610 ns; Loc. = LC_X20_Y7_N8; Fanout = 1; COMB Node = 'LessThan5~504'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.333 ns" { LessThan5~502 LessThan5~504 } "NODE_NAME" } } { "myled.vhd" "" { Text "D:/STUDY/qt/myled/myled.vhd" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.114 ns) 3.906 ns LessThan5~505 6 COMB LC_X20_Y7_N9 29 " "Info: 6: + IC(0.182 ns) + CELL(0.114 ns) = 3.906 ns; Loc. = LC_X20_Y7_N9; Fanout = 29; COMB Node = 'LessThan5~505'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.296 ns" { LessThan5~504 LessThan5~505 } "NODE_NAME" } } { "myled.vhd" "" { Text "D:/STUDY/qt/myled/myled.vhd" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.336 ns) + CELL(1.112 ns) 6.354 ns counter\[7\] 7 REG LC_X20_Y9_N9 4 " "Info: 7: + IC(1.336 ns) + CELL(1.112 ns) = 6.354 ns; Loc. = LC_X20_Y9_N9; Fanout = 4; REG Node = 'counter\[7\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.448 ns" { LessThan5~505 counter[7] } "NODE_NAME" } } { "myled.vhd" "" { Text "D:/STUDY/qt/myled/myled.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.860 ns ( 29.27 % ) " "Info: Total cell delay = 1.860 ns ( 29.27 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.494 ns ( 70.73 % ) " "Info: Total interconnect delay = 4.494 ns ( 70.73 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.354 ns" { counter[10] LessThan5~500 LessThan5~501 LessThan5~502 LessThan5~504 LessThan5~505 counter[7] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.354 ns" { counter[10] {} LessThan5~500 {} LessThan5~501 {} LessThan5~502 {} LessThan5~504 {} LessThan5~505 {} counter[7] {} } { 0.000ns 1.235ns 0.182ns 0.340ns 1.219ns 0.182ns 1.336ns } { 0.000ns 0.292ns 0.114ns 0.114ns 0.114ns 0.114ns 1.112ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.782 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.782 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_16 29 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 29; CLK Node = 'clk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "myled.vhd" "" { Text "D:/STUDY/qt/myled/myled.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.602 ns) + CELL(0.711 ns) 2.782 ns counter\[7\] 2 REG LC_X20_Y9_N9 4 " "Info: 2: + IC(0.602 ns) + CELL(0.711 ns) = 2.782 ns; Loc. = LC_X20_Y9_N9; Fanout = 4; REG Node = 'counter\[7\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.313 ns" { clk counter[7] } "NODE_NAME" } } { "myled.vhd" "" { Text "D:/STUDY/qt/myled/myled.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 78.36 % ) " "Info: Total cell delay = 2.180 ns ( 78.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.602 ns ( 21.64 % ) " "Info: Total interconnect delay = 0.602 ns ( 21.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { clk counter[7] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { clk {} clk~out0 {} counter[7] {} } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.782 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.782 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_16 29 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 29; CLK Node = 'clk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "myled.vhd" "" { Text "D:/STUDY/qt/myled/myled.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.602 ns) + CELL(0.711 ns) 2.782 ns counter\[10\] 2 REG LC_X20_Y8_N2 7 " "Info: 2: + IC(0.602 ns) + CELL(0.711 ns) = 2.782 ns; Loc. = LC_X20_Y8_N2; Fanout = 7; REG Node = 'counter\[10\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.313 ns" { clk counter[10] } "NODE_NAME" } } { "myled.vhd" "" { Text "D:/STUDY/qt/myled/myled.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 78.36 % ) " "Info: Total cell delay = 2.180 ns ( 78.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.602 ns ( 21.64 % ) " "Info: Total interconnect delay = 0.602 ns ( 21.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { clk counter[10] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { clk {} clk~out0 {} counter[10] {} } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { clk counter[7] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { clk {} clk~out0 {} counter[7] {} } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { clk counter[10] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { clk {} clk~out0 {} counter[10] {} } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "myled.vhd" "" { Text "D:/STUDY/qt/myled/myled.vhd" 22 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "myled.vhd" "" { Text "D:/STUDY/qt/myled/myled.vhd" 22 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.354 ns" { counter[10] LessThan5~500 LessThan5~501 LessThan5~502 LessThan5~504 LessThan5~505 counter[7] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.354 ns" { counter[10] {} LessThan5~500 {} LessThan5~501 {} LessThan5~502 {} LessThan5~504 {} LessThan5~505 {} counter[7] {} } { 0.000ns 1.235ns 0.182ns 0.340ns 1.219ns 0.182ns 1.336ns } { 0.000ns 0.292ns 0.114ns 0.114ns 0.114ns 0.114ns 1.112ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { clk counter[7] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { clk {} clk~out0 {} counter[7] {} } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { clk counter[10] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { clk {} clk~out0 {} counter[10] {} } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk led2 ledtmp2 7.372 ns register " "Info: tco from clock \"clk\" to destination pin \"led2\" through register \"ledtmp2\" is 7.372 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.782 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.782 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_16 29 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 29; CLK Node = 'clk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "myled.vhd" "" { Text "D:/STUDY/qt/myled/myled.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.602 ns) + CELL(0.711 ns) 2.782 ns ledtmp2 2 REG LC_X20_Y9_N1 3 " "Info: 2: + IC(0.602 ns) + CELL(0.711 ns) = 2.782 ns; Loc. = LC_X20_Y9_N1; Fanout = 3; REG Node = 'ledtmp2'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.313 ns" { clk ledtmp2 } "NODE_NAME" } } { "myled.vhd" "" { Text "D:/STUDY/qt/myled/myled.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 78.36 % ) " "Info: Total cell delay = 2.180 ns ( 78.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.602 ns ( 21.64 % ) " "Info: Total interconnect delay = 0.602 ns ( 21.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { clk ledtmp2 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { clk {} clk~out0 {} ledtmp2 {} } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "myled.vhd" "" { Text "D:/STUDY/qt/myled/myled.vhd" 22 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.366 ns + Longest register pin " "Info: + Longest register to pin delay is 4.366 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ledtmp2 1 REG LC_X20_Y9_N1 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X20_Y9_N1; Fanout = 3; REG Node = 'ledtmp2'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { ledtmp2 } "NODE_NAME" } } { "myled.vhd" "" { Text "D:/STUDY/qt/myled/myled.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.242 ns) + CELL(2.124 ns) 4.366 ns led2 2 PIN PIN_107 0 " "Info: 2: + IC(2.242 ns) + CELL(2.124 ns) = 4.366 ns; Loc. = PIN_107; Fanout = 0; PIN Node = 'led2'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.366 ns" { ledtmp2 led2 } "NODE_NAME" } } { "myled.vhd" "" { Text "D:/STUDY/qt/myled/myled.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.124 ns ( 48.65 % ) " "Info: Total cell delay = 2.124 ns ( 48.65 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.242 ns ( 51.35 % ) " "Info: Total interconnect delay = 2.242 ns ( 51.35 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.366 ns" { ledtmp2 led2 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.366 ns" { ledtmp2 {} led2 {} } { 0.000ns 2.242ns } { 0.000ns 2.124ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.782 ns" { clk ledtmp2 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.782 ns" { clk {} clk~out0 {} ledtmp2 {} } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.366 ns" { ledtmp2 led2 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.366 ns" { ledtmp2 {} led2 {} } { 0.000ns 2.242ns } { 0.000ns 2.124ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "110 " "Info: Allocated 110 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon Oct 06 16:19:50 2008 " "Info: Processing ended: Mon Oct 06 16:19:50 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}