myled.tan.rpt

EP1C3144的点灯基本程序

; N/A                                     ; 177.40 MHz ( period = 5.637 ns )                    ; counter[15] ; counter[19] ; clk        ; clk      ; None                        ; None                      ; 5.376 ns                ;
; N/A                                     ; 177.40 MHz ( period = 5.637 ns )                    ; counter[15] ; counter[18] ; clk        ; clk      ; None                        ; None                      ; 5.376 ns                ;
; N/A                                     ; 177.40 MHz ( period = 5.637 ns )                    ; counter[15] ; counter[23] ; clk        ; clk      ; None                        ; None                      ; 5.376 ns                ;
; N/A                                     ; 177.40 MHz ( period = 5.637 ns )                    ; counter[15] ; counter[24] ; clk        ; clk      ; None                        ; None                      ; 5.376 ns                ;
; N/A                                     ; 177.40 MHz ( period = 5.637 ns )                    ; counter[15] ; counter[25] ; clk        ; clk      ; None                        ; None                      ; 5.376 ns                ;
; N/A                                     ; 177.71 MHz ( period = 5.627 ns )                    ; counter[11] ; ledtmp2     ; clk        ; clk      ; None                        ; None                      ; 5.366 ns                ;
; N/A                                     ; 178.54 MHz ( period = 5.601 ns )                    ; counter[13] ; ledtmp1     ; clk        ; clk      ; None                        ; None                      ; 5.340 ns                ;
; N/A                                     ; 178.86 MHz ( period = 5.591 ns )                    ; counter[15] ; counter[17] ; clk        ; clk      ; None                        ; None                      ; 5.330 ns                ;
; N/A                                     ; 178.86 MHz ( period = 5.591 ns )                    ; counter[15] ; counter[8]  ; clk        ; clk      ; None                        ; None                      ; 5.330 ns                ;
; N/A                                     ; 178.86 MHz ( period = 5.591 ns )                    ; counter[15] ; counter[9]  ; clk        ; clk      ; None                        ; None                      ; 5.330 ns                ;
; N/A                                     ; 178.86 MHz ( period = 5.591 ns )                    ; counter[15] ; counter[11] ; clk        ; clk      ; None                        ; None                      ; 5.330 ns                ;
; N/A                                     ; 178.86 MHz ( period = 5.591 ns )                    ; counter[15] ; counter[10] ; clk        ; clk      ; None                        ; None                      ; 5.330 ns                ;
; N/A                                     ; 178.86 MHz ( period = 5.591 ns )                    ; counter[15] ; counter[13] ; clk        ; clk      ; None                        ; None                      ; 5.330 ns                ;
; N/A                                     ; 178.86 MHz ( period = 5.591 ns )                    ; counter[15] ; counter[12] ; clk        ; clk      ; None                        ; None                      ; 5.330 ns                ;
; N/A                                     ; 178.86 MHz ( period = 5.591 ns )                    ; counter[15] ; counter[16] ; clk        ; clk      ; None                        ; None                      ; 5.330 ns                ;
; N/A                                     ; 178.86 MHz ( period = 5.591 ns )                    ; counter[15] ; counter[15] ; clk        ; clk      ; None                        ; None                      ; 5.330 ns                ;
; N/A                                     ; 178.86 MHz ( period = 5.591 ns )                    ; counter[15] ; counter[14] ; clk        ; clk      ; None                        ; None                      ; 5.330 ns                ;
; N/A                                     ; 179.02 MHz ( period = 5.586 ns )                    ; counter[17] ; ledtmp2     ; clk        ; clk      ; None                        ; None                      ; 5.325 ns                ;
; N/A                                     ; 179.99 MHz ( period = 5.556 ns )                    ; counter[9]  ; ledtmp3     ; clk        ; clk      ; None                        ; None                      ; 5.295 ns                ;
; N/A                                     ; 180.15 MHz ( period = 5.551 ns )                    ; counter[7]  ; ledtmp2     ; clk        ; clk      ; None                        ; None                      ; 5.290 ns                ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;             ;             ;            ;          ;                             ;                           ;                         ;
+-----------------------------------------+-----------------------------------------------------+-------------+-------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+-----------------------------------------------------------------+
; tco                                                             ;
+-------+--------------+------------+---------+------+------------+
; Slack ; Required tco ; Actual tco ; From    ; To   ; From Clock ;
+-------+--------------+------------+---------+------+------------+
; N/A   ; None         ; 7.276 ns   ; ledtmp1 ; led1 ; clk        ;
; N/A   ; None         ; 6.858 ns   ; ledtmp2 ; led2 ; clk        ;
; N/A   ; None         ; 6.826 ns   ; ledtmp3 ; led3 ; clk        ;
+-------+--------------+------------+---------+------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Mon Oct 06 16:24:44 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off myled -c myled --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 158.38 MHz between source register "counter[9]" and destination register "ledtmp1" (period= 6.314 ns)
    Info: + Longest register to register delay is 6.053 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X20_Y12_N1; Fanout = 7; REG Node = 'counter[9]'
        Info: 2: + IC(1.267 ns) + CELL(0.590 ns) = 1.857 ns; Loc. = LC_X21_Y13_N1; Fanout = 1; COMB Node = 'LessThan0~507'
        Info: 3: + IC(0.421 ns) + CELL(0.114 ns) = 2.392 ns; Loc. = LC_X21_Y13_N0; Fanout = 1; COMB Node = 'LessThan0~508'
        Info: 4: + IC(1.246 ns) + CELL(0.114 ns) = 3.752 ns; Loc. = LC_X21_Y12_N9; Fanout = 1; COMB Node = 'LessThan0~509'
        Info: 5: + IC(1.128 ns) + CELL(0.114 ns) = 4.994 ns; Loc. = LC_X22_Y13_N8; Fanout = 2; COMB Node = 'LessThan0~510'
        Info: 6: + IC(0.750 ns) + CELL(0.309 ns) = 6.053 ns; Loc. = LC_X21_Y13_N6; Fanout = 2; REG Node = 'ledtmp1'
        Info: Total cell delay = 1.241 ns ( 20.50 % )
        Info: Total interconnect delay = 4.812 ns ( 79.50 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 2.782 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 29; CLK Node = 'clk'
            Info: 2: + IC(0.602 ns) + CELL(0.711 ns) = 2.782 ns; Loc. = LC_X21_Y13_N6; Fanout = 2; REG Node = 'ledtmp1'
            Info: Total cell delay = 2.180 ns ( 78.36 % )
            Info: Total interconnect delay = 0.602 ns ( 21.64 % )
        Info: - Longest clock path from clock "clk" to source register is 2.782 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 29; CLK Node = 'clk'
            Info: 2: + IC(0.602 ns) + CELL(0.711 ns) = 2.782 ns; Loc. = LC_X20_Y12_N1; Fanout = 7; REG Node = 'counter[9]'
            Info: Total cell delay = 2.180 ns ( 78.36 % )
            Info: Total interconnect delay = 0.602 ns ( 21.64 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Micro setup delay of destination is 0.037 ns
Info: tco from clock "clk" to destination pin "led1" through register "ledtmp1" is 7.276 ns
    Info: + Longest clock path from clock "clk" to source register is 2.782 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 29; CLK Node = 'clk'
        Info: 2: + IC(0.602 ns) + CELL(0.711 ns) = 2.782 ns; Loc. = LC_X21_Y13_N6; Fanout = 2; REG Node = 'ledtmp1'
        Info: Total cell delay = 2.180 ns ( 78.36 % )
        Info: Total interconnect delay = 0.602 ns ( 21.64 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 4.270 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X21_Y13_N6; Fanout = 2; REG Node = 'ledtmp1'
        Info: 2: + IC(2.146 ns) + CELL(2.124 ns) = 4.270 ns; Loc. = PIN_106; Fanout = 0; PIN Node = 'led1'
        Info: Total cell delay = 2.124 ns ( 49.74 % )
        Info: Total interconnect delay = 2.146 ns ( 50.26 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 110 megabytes of memory during processing
    Info: Processing ended: Mon Oct 06 16:24:48 2008
    Info: Elapsed time: 00:00:04