📄 myled.vhd.bak
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY myled IS
PORT (clk:in std_logic;
led1:out std_logic;
led2:out std_logic;
led3:out std_logic
);
END;
ARCHITECTURE ledtst OF myled IS
SIGNAL counter:integer range 0 to 60000000;
signal ledtmp1:std_logic;
signal ledtmp2:std_logic;
signal ledtmp3:std_logic;
BEGIN
PROCESS(clk)
BEGIN
if (clk'event and clk='1') then
counter<=counter+1;
if(counter<10000000) then
ledtmp1<='1';
end if;
if(counter>=10000000 and counter<20000000) then
ledtmp2<='1';
end if;
if(counter>=20000000 and counter<30000000) then
ledtmp3<='1';
end if;
if(counter>=40000000) then
counter<=0;
ledtmp1<='0';
ledtmp2<='0';
ledtmp3<='0';
end if;
end if;
end process;
led1<=ledtmp1;
led2<=ledtmp2;
led3<=ledtmp3;
end ledtst;
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