lcd_v.tan.qmsg

用EPM1270实现的1602液晶驱动Verilog

{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "lcd:inst1\|state.IDLE lcd:inst1\|always4~2 mclk 127 ps " "Info: Found hold time violation between source  pin or register \"lcd:inst1\|state.IDLE\" and destination pin or register \"lcd:inst1\|always4~2\" for clock \"mclk\" (Hold time is 127 ps)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "1.517 ns + Largest " "Info: + Largest clock skew is 1.517 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "mclk destination 28.897 ns + Longest register " "Info: + Longest clock path from clock \"mclk\" to destination register is 28.897 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns mclk 1 CLK PIN_127 4 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_127; Fanout = 4; CLK Node = 'mclk'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_v" "UNKNOWN" "V1" "E:/PLD/调试/接口实验/1602LCD/db/lcd_v.quartus_db" { Floorplan "E:/PLD/调试/接口实验/1602LCD/" "" "" { mclk } "NODE_NAME" } "" } } { "lcd_v.bdf" "" { Schematic "E:/PLD/调试/接口实验/1602LCD/lcd_v.bdf" { { 48 -96 72 64 "mclk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.273 ns) + CELL(1.294 ns) 7.699 ns div16:inst\|count\[3\] 2 REG LC_X11_Y4_N2 17 " "Info: 2: + IC(5.273 ns) + CELL(1.294 ns) = 7.699 ns; Loc. = LC_X11_Y4_N2; Fanout = 17; REG Node = 'div16:inst\|count\[3\]'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_v" "UNKNOWN" "V1" "E:/PLD/调试/接口实验/1602LCD/db/lcd_v.quartus_db" { Floorplan "E:/PLD/调试/接口实验/1602LCD/" "" "6.567 ns" { mclk div16:inst|count[3] } "NODE_NAME" } "" } } { "DIV16.v" "" { Text "E:/PLD/调试/接口实验/1602LCD/DIV16.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.916 ns) + CELL(1.294 ns) 12.909 ns lcd:inst1\|clkcnt\[4\] 3 REG LC_X13_Y6_N6 4 " "Info: 3: + IC(3.916 ns) + CELL(1.294 ns) = 12.909 ns; Loc. = LC_X13_Y6_N6; Fanout = 4; REG Node = 'lcd:inst1\|clkcnt\[4\]'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_v" "UNKNOWN" "V1" "E:/PLD/调试/接口实验/1602LCD/db/lcd_v.quartus_db" { Floorplan "E:/PLD/调试/接口实验/1602LCD/" "" "5.210 ns" { div16:inst|count[3] lcd:inst1|clkcnt[4] } "NODE_NAME" } "" } } { "lcd.v" "" { Text "E:/PLD/调试/接口实验/1602LCD/lcd.v" 99 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.946 ns) + CELL(0.914 ns) 14.769 ns rtl~107 4 COMB LC_X13_Y6_N0 1 " "Info: 4: + IC(0.946 ns) + CELL(0.914 ns) = 14.769 ns; Loc. = LC_X13_Y6_N0; Fanout = 1; COMB Node = 'rtl~107'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_v" "UNKNOWN" "V1" "E:/PLD/调试/接口实验/1602LCD/db/lcd_v.quartus_db" { Floorplan "E:/PLD/调试/接口实验/1602LCD/" "" "1.860 ns" { lcd:inst1|clkcnt[4] rtl~107 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.709 ns) + CELL(0.914 ns) 17.392 ns rtl~110 5 COMB LC_X15_Y6_N2 2 " "Info: 5: + IC(1.709 ns) + CELL(0.914 ns) = 17.392 ns; Loc. = LC_X15_Y6_N2; Fanout = 2; COMB Node = 'rtl~110'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_v" "UNKNOWN" "V1" "E:/PLD/调试/接口实验/1602LCD/db/lcd_v.quartus_db" { Floorplan "E:/PLD/调试/接口实验/1602LCD/" "" "2.623 ns" { rtl~107 rtl~110 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.662 ns) + CELL(1.294 ns) 19.348 ns lcd:inst1\|clkdiv 6 REG LC_X15_Y6_N5 3 " "Info: 6: + IC(0.662 ns) + CELL(1.294 ns) = 19.348 ns; Loc. = LC_X15_Y6_N5; Fanout = 3; REG Node = 'lcd:inst1\|clkdiv'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_v" "UNKNOWN" "V1" "E:/PLD/调试/接口实验/1602LCD/db/lcd_v.quartus_db" { Floorplan "E:/PLD/调试/接口实验/1602LCD/" "" "1.956 ns" { rtl~110 lcd:inst1|clkdiv } "NODE_NAME" } "" } } { "lcd.v" "" { Text "E:/PLD/调试/接口实验/1602LCD/lcd.v" 114 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.309 ns) + CELL(1.294 ns) 24.951 ns lcd:inst1\|clk_int 7 REG LC_X12_Y3_N2 28 " "Info: 7: + IC(4.309 ns) + CELL(1.294 ns) = 24.951 ns; Loc. = LC_X12_Y3_N2; Fanout = 28; REG Node = 'lcd:inst1\|clk_int'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_v" "UNKNOWN" "V1" "E:/PLD/调试/接口实验/1602LCD/db/lcd_v.quartus_db" { Floorplan "E:/PLD/调试/接口实验/1602LCD/" "" "5.603 ns" { lcd:inst1|clkdiv lcd:inst1|clk_int } "NODE_NAME" } "" } } { "lcd.v" "" { Text "E:/PLD/调试/接口实验/1602LCD/lcd.v" 121 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.028 ns) + CELL(0.918 ns) 28.897 ns lcd:inst1\|always4~2 8 REG LC_X11_Y10_N3 8 " "Info: 8: + IC(3.028 ns) + CELL(0.918 ns) = 28.897 ns; Loc. = LC_X11_Y10_N3; Fanout = 8; REG Node = 'lcd:inst1\|always4~2'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_v" "UNKNOWN" "V1" "E:/PLD/调试/接口实验/1602LCD/db/lcd_v.quartus_db" { Floorplan "E:/PLD/调试/接口实验/1602LCD/" "" "3.946 ns" { lcd:inst1|clk_int lcd:inst1|always4~2 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "9.054 ns ( 31.33 % ) " "Info: Total cell delay = 9.054 ns ( 31.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "19.843 ns ( 68.67 % ) " "Info: Total interconnect delay = 19.843 ns ( 68.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_v" "UNKNOWN" "V1" "E:/PLD/调试/接口实验/1602LCD/db/lcd_v.quartus_db" { Floorplan "E:/PLD/调试/接口实验/1602LCD/" "" "28.897 ns" { mclk div16:inst|count[3] lcd:inst1|clkcnt[4] rtl~107 rtl~110 lcd:inst1|clkdiv lcd:inst1|clk_int lcd:inst1|always4~2 } "NODE_NAME" } "" } } { "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "28.897 ns" { mclk mclk~combout div16:inst|count[3] lcd:inst1|clkcnt[4] rtl~107 rtl~110 lcd:inst1|clkdiv lcd:inst1|clk_int lcd:inst1|always4~2 } { 0.000ns 0.000ns 5.273ns 3.916ns 0.946ns 1.709ns 0.662ns 4.309ns 3.028ns } { 0.000ns 1.132ns 1.294ns 1.294ns 0.914ns 0.914ns 1.294ns 1.294ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "mclk source 27.380 ns - Shortest register " "Info: - Shortest clock path from clock \"mclk\" to source register is 27.380 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns mclk 1 CLK PIN_127 4 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_127; Fanout = 4; CLK Node = 'mclk'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_v" "UNKNOWN" "V1" "E:/PLD/调试/接口实验/1602LCD/db/lcd_v.quartus_db" { Floorplan "E:/PLD/调试/接口实验/1602LCD/" "" "" { mclk } "NODE_NAME" } "" } } { "lcd_v.bdf" "" { Schematic "E:/PLD/调试/接口实验/1602LCD/lcd_v.bdf" { { 48 -96 72 64 "mclk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.273 ns) + CELL(1.294 ns) 7.699 ns div16:inst\|count\[3\] 2 REG LC_X11_Y4_N2 17 " "Info: 2: + IC(5.273 ns) + CELL(1.294 ns) = 7.699 ns; Loc. = LC_X11_Y4_N2; Fanout = 17; REG Node = 'div16:inst\|count\[3\]'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_v" "UNKNOWN" "V1" "E:/PLD/调试/接口实验/1602LCD/db/lcd_v.quartus_db" { Floorplan "E:/PLD/调试/接口实验/1602LCD/" "" "6.567 ns" { mclk div16:inst|count[3] } "NODE_NAME" } "" } } { "DIV16.v" "" { Text "E:/PLD/调试/接口实验/1602LCD/DIV16.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.916 ns) + CELL(1.294 ns) 12.909 ns lcd:inst1\|clkcnt\[10\] 3 REG LC_X14_Y6_N2 4 " "Info: 3: + IC(3.916 ns) + CELL(1.294 ns) = 12.909 ns; Loc. = LC_X14_Y6_N2; Fanout = 4; REG Node = 'lcd:inst1\|clkcnt\[10\]'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_v" "UNKNOWN" "V1" "E:/PLD/调试/接口实验/1602LCD/db/lcd_v.quartus_db" { Floorplan "E:/PLD/调试/接口实验/1602LCD/" "" "5.210 ns" { div16:inst|count[3] lcd:inst1|clkcnt[10] } "NODE_NAME" } "" } } { "lcd.v" "" { Text "E:/PLD/调试/接口实验/1602LCD/lcd.v" 99 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.937 ns) + CELL(0.200 ns) 14.046 ns rtl~108 4 COMB LC_X14_Y6_N8 1 " "Info: 4: + IC(0.937 ns) + CELL(0.200 ns) = 14.046 ns; Loc. = LC_X14_Y6_N8; Fanout = 1; COMB Node = 'rtl~108'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_v" "UNKNOWN" "V1" "E:/PLD/调试/接口实验/1602LCD/db/lcd_v.quartus_db" { Floorplan "E:/PLD/调试/接口实验/1602LCD/" "" "1.137 ns" { lcd:inst1|clkcnt[10] rtl~108 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.629 ns) + CELL(0.200 ns) 15.875 ns rtl~110 5 COMB LC_X15_Y6_N2 2 " "Info: 5: + IC(1.629 ns) + CELL(0.200 ns) = 15.875 ns; Loc. = LC_X15_Y6_N2; Fanout = 2; COMB Node = 'rtl~110'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_v" "UNKNOWN" "V1" "E:/PLD/调试/接口实验/1602LCD/db/lcd_v.quartus_db" { Floorplan "E:/PLD/调试/接口实验/1602LCD/" "" "1.829 ns" { rtl~108 rtl~110 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.662 ns) + CELL(1.294 ns) 17.831 ns lcd:inst1\|clkdiv 6 REG LC_X15_Y6_N5 3 " "Info: 6: + IC(0.662 ns) + CELL(1.294 ns) = 17.831 ns; Loc. = LC_X15_Y6_N5; Fanout = 3; REG Node = 'lcd:inst1\|clkdiv'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_v" "UNKNOWN" "V1" "E:/PLD/调试/接口实验/1602LCD/db/lcd_v.quartus_db" { Floorplan "E:/PLD/调试/接口实验/1602LCD/" "" "1.956 ns" { rtl~110 lcd:inst1|clkdiv } "NODE_NAME" } "" } } { "lcd.v" "" { Text "E:/PLD/调试/接口实验/1602LCD/lcd.v" 114 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.309 ns) + CELL(1.294 ns) 23.434 ns lcd:inst1\|clk_int 7 REG LC_X12_Y3_N2 28 " "Info: 7: + IC(4.309 ns) + CELL(1.294 ns) = 23.434 ns; Loc. = LC_X12_Y3_N2; Fanout = 28; REG Node = 'lcd:inst1\|clk_int'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_v" "UNKNOWN" "V1" "E:/PLD/调试/接口实验/1602LCD/db/lcd_v.quartus_db" { Floorplan "E:/PLD/调试/接口实验/1602LCD/" "" "5.603 ns" { lcd:inst1|clkdiv lcd:inst1|clk_int } "NODE_NAME" } "" } } { "lcd.v" "" { Text "E:/PLD/调试/接口实验/1602LCD/lcd.v" 121 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.028 ns) + CELL(0.918 ns) 27.380 ns lcd:inst1\|state.IDLE 8 REG LC_X11_Y10_N7 5 " "Info: 8: + IC(3.028 ns) + CELL(0.918 ns) = 27.380 ns; Loc. = LC_X11_Y10_N7; Fanout = 5; REG Node = 'lcd:inst1\|state.IDLE'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_v" "UNKNOWN" "V1" "E:/PLD/调试/接口实验/1602LCD/db/lcd_v.quartus_db" { Floorplan "E:/PLD/调试/接口实验/1602LCD/" "" "3.946 ns" { lcd:inst1|clk_int lcd:inst1|state.IDLE } "NODE_NAME" } "" } } { "lcd.v" "" { Text "E:/PLD/调试/接口实验/1602LCD/lcd.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.626 ns ( 27.85 % ) " "Info: Total cell delay = 7.626 ns ( 27.85 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "19.754 ns ( 72.15 % ) " "Info: Total interconnect delay = 19.754 ns ( 72.15 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_v" "UNKNOWN" "V1" "E:/PLD/调试/接口实验/1602LCD/db/lcd_v.quartus_db" { Floorplan "E:/PLD/调试/接口实验/1602LCD/" "" "27.380 ns" { mclk div16:inst|count[3] lcd:inst1|clkcnt[10] rtl~108 rtl~110 lcd:inst1|clkdiv lcd:inst1|clk_int lcd:inst1|state.IDLE } "NODE_NAME" } "" } } { "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "27.380 ns" { mclk mclk~combout div16:inst|count[3] lcd:inst1|clkcnt[10] rtl~108 rtl~110 lcd:inst1|clkdiv lcd:inst1|clk_int lcd:inst1|state.IDLE } { 0.000ns 0.000ns 5.273ns 3.916ns 0.937ns 1.629ns 0.662ns 4.309ns 3.028ns } { 0.000ns 1.132ns 1.294ns 1.294ns 0.200ns 0.200ns 1.294ns 1.294ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_v" "UNKNOWN" "V1" "E:/PLD/调试/接口实验/1602LCD/db/lcd_v.quartus_db" { Floorplan "E:/PLD/调试/接口实验/1602LCD/" "" "28.897 ns" { mclk div16:inst|count[3] lcd:inst1|clkcnt[4] rtl~107 rtl~110 lcd:inst1|clkdiv lcd:inst1|clk_int lcd:inst1|always4~2 } "NODE_NAME" } "" } } { "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "28.897 ns" { mclk mclk~combout div16:inst|count[3] lcd:inst1|clkcnt[4] rtl~107 rtl~110 lcd:inst1|clkdiv lcd:inst1|clk_int lcd:inst1|always4~2 } { 0.000ns 0.000ns 5.273ns 3.916ns 0.946ns 1.709ns 0.662ns 4.309ns 3.028ns } { 0.000ns 1.132ns 1.294ns 1.294ns 0.914ns 0.914ns 1.294ns 1.294ns 0.918ns } } } { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_v" "UNKNOWN" "V1" "E:/PLD/调试/接口实验/1602LCD/db/lcd_v.quartus_db" { Floorplan "E:/PLD/调试/接口实验/1602LCD/" "" "27.380 ns" { mclk div16:inst|count[3] lcd:inst1|clkcnt[10] rtl~108 rtl~110 lcd:inst1|clkdiv lcd:inst1|clk_int lcd:inst1|state.IDLE } "NODE_NAME" } "" } } { "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "27.380 ns" { mclk mclk~combout div16:inst|count[3] lcd:inst1|clkcnt[10] rtl~108 rtl~110 lcd:inst1|clkdiv lcd:inst1|clk_int lcd:inst1|state.IDLE } { 0.000ns 0.000ns 5.273ns 3.916ns 0.937ns 1.629ns 0.662ns 4.309ns 3.028ns } { 0.000ns 1.132ns 1.294ns 1.294ns 0.200ns 0.200ns 1.294ns 1.294ns 0.918ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns - " "Info: - Micro clock to output delay of source is 0.376 ns" {  } { { "lcd.v" "" { Text "E:/PLD/调试/接口实验/1602LCD/lcd.v" 8 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.235 ns - Shortest register register " "Info: - Shortest register to register delay is 1.235 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lcd:inst1\|state.IDLE 1 REG LC_X11_Y10_N7 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X11_Y10_N7; Fanout = 5; REG Node = 'lcd:inst1\|state.IDLE'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_v" "UNKNOWN" "V1" "E:/PLD/调试/接口实验/1602LCD/db/lcd_v.quartus_db" { Floorplan "E:/PLD/调试/接口实验/1602LCD/" "" "" { lcd:inst1|state.IDLE } "NODE_NAME" } "" } } { "lcd.v" "" { Text "E:/PLD/调试/接口实验/1602LCD/lcd.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.955 ns) + CELL(0.280 ns) 1.235 ns lcd:inst1\|always4~2 2 REG LC_X11_Y10_N3 8 " "Info: 2: + IC(0.955 ns) + CELL(0.280 ns) = 1.235 ns; Loc. = LC_X11_Y10_N3; Fanout = 8; REG Node = 'lcd:inst1\|always4~2'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_v" "UNKNOWN" "V1" "E:/PLD/调试/接口实验/1602LCD/db/lcd_v.quartus_db" { Floorplan "E:/PLD/调试/接口实验/1602LCD/" "" "1.235 ns" { lcd:inst1|state.IDLE lcd:inst1|always4~2 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.280 ns ( 22.67 % ) " "Info: Total cell delay = 0.280 ns ( 22.67 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.955 ns ( 77.33 % ) " "Info: Total interconnect delay = 0.955 ns ( 77.33 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_v" "UNKNOWN" "V1" "E:/PLD/调试/接口实验/1602LCD/db/lcd_v.quartus_db" { Floorplan "E:/PLD/调试/接口实验/1602LCD/" "" "1.235 ns" { lcd:inst1|state.IDLE lcd:inst1|always4~2 } "NODE_NAME" } "" } } { "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "1.235 ns" { lcd:inst1|state.IDLE lcd:inst1|always4~2 } { 0.000ns 0.955ns } { 0.000ns 0.280ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.221 ns + " "Info: + Micro hold delay of destination is 0.221 ns" {  } {  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0}  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_v" "UNKNOWN" "V1" "E:/PLD/调试/接口实验/1602LCD/db/lcd_v.quartus_db" { Floorplan "E:/PLD/调试/接口实验/1602LCD/" "" "28.897 ns" { mclk div16:inst|count[3] lcd:inst1|clkcnt[4] rtl~107 rtl~110 lcd:inst1|clkdiv lcd:inst1|clk_int lcd:inst1|always4~2 } "NODE_NAME" } "" } } { "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "28.897 ns" { mclk mclk~combout div16:inst|count[3] lcd:inst1|clkcnt[4] rtl~107 rtl~110 lcd:inst1|clkdiv lcd:inst1|clk_int lcd:inst1|always4~2 } { 0.000ns 0.000ns 5.273ns 3.916ns 0.946ns 1.709ns 0.662ns 4.309ns 3.028ns } { 0.000ns 1.132ns 1.294ns 1.294ns 0.914ns 0.914ns 1.294ns 1.294ns 0.918ns } } } { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_v" "UNKNOWN" "V1" "E:/PLD/调试/接口实验/1602LCD/db/lcd_v.quartus_db" { Floorplan "E:/PLD/调试/接口实验/1602LCD/" "" "27.380 ns" { mclk div16:inst|count[3] lcd:inst1|clkcnt[10] rtl~108 rtl~110 lcd:inst1|clkdiv lcd:inst1|clk_int lcd:inst1|state.IDLE } "NODE_NAME" } "" } } { "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "27.380 ns" { mclk mclk~combout div16:inst|count[3] lcd:inst1|clkcnt[10] rtl~108 rtl~110 lcd:inst1|clkdiv lcd:inst1|clk_int lcd:inst1|state.IDLE } { 0.000ns 0.000ns 5.273ns 3.916ns 0.937ns 1.629ns 0.662ns 4.309ns 3.028ns } { 0.000ns 1.132ns 1.294ns 1.294ns 0.200ns 0.200ns 1.294ns 1.294ns 0.918ns } } } { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_v" "UNKNOWN" "V1" "E:/PLD/调试/接口实验/1602LCD/db/lcd_v.quartus_db" { Floorplan "E:/PLD/调试/接口实验/1602LCD/" "" "1.235 ns" { lcd:inst1|state.IDLE lcd:inst1|always4~2 } "NODE_NAME" } "" } } { "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "1.235 ns" { lcd:inst1|state.IDLE lcd:inst1|always4~2 } { 0.000ns 0.955ns } { 0.000ns 0.280ns } } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "lcd:inst1\|clkcnt\[0\] rst mclk -2.209 ns register " "Info: tsu for register \"lcd:inst1\|clkcnt\[0\]\" (data pin = \"rst\", clock pin = \"mclk\") is -2.209 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.991 ns + Longest pin register " "Info: + Longest pin to register delay is 9.991 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns rst 1 PIN PIN_110 27 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_110; Fanout = 27; PIN Node = 'rst'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_v" "UNKNOWN" "V1" "E:/PLD/调试/接口实验/1602LCD/db/lcd_v.quartus_db" { Floorplan "E:/PLD/调试/接口实验/1602LCD/" "" "" { rst } "NODE_NAME" } "" } } { "lcd_v.bdf" "" { Schematic "E:/PLD/调试/接口实验/1602LCD/lcd_v.bdf" { { 64 -96 72 80 "rst" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.828 ns) + CELL(0.511 ns) 6.471 ns lcd:inst1\|clkcnt\[9\]~424 2 COMB LC_X15_Y6_N3 16 " "Info: 2: + IC(4.828 ns) + CELL(0.511 ns) = 6.471 ns; Loc. = LC_X15_Y6_N3; Fanout = 16; COMB Node = 'lcd:inst1\|clkcnt\[9\]~424'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_v" "UNKNOWN" "V1" "E:/PLD/调试/接口实验/1602LCD/db/lcd_v.quartus_db" { Floorplan "E:/PLD/调试/接口实验/1602LCD/" "" "5.339 ns" { rst lcd:inst1|clkcnt[9]~424 } "NODE_NAME" } "" } } { "lcd.v" "" { Text "E:/PLD/调试/接口实验/1602LCD/lcd.v" 99 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.760 ns) + CELL(1.760 ns) 9.991 ns lcd:inst1\|clkcnt\[0\] 3 REG LC_X13_Y6_N2 4 " "Info: 3: + IC(1.760 ns) + CELL(1.760 ns) = 9.991 ns; Loc. = LC_X13_Y6_N2; Fanout = 4; REG Node = 'lcd:inst1\|clkcnt\[0\]'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_v" "UNKNOWN" "V1" "E:/PLD/调试/接口实验/1602LCD/db/lcd_v.quartus_db" { Floorplan "E:/PLD/调试/接口实验/1602LCD/" "" "3.520 ns" { lcd:inst1|clkcnt[9]~424 lcd:inst1|clkcnt[0] } "NODE_NAME" } "" } } { "lcd.v" "" { Text "E:/PLD/调试/接口实验/1602LCD/lcd.v" 99 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.403 ns ( 34.06 % ) " "Info: Total cell delay = 3.403 ns ( 34.06 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.588 ns ( 65.94 % ) " "Info: Total interconnect delay = 6.588 ns ( 65.94 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_v" "UNKNOWN" "V1" "E:/PLD/调试/接口实验/1602LCD/db/lcd_v.quartus_db" { Floorplan "E:/PLD/调试/接口实验/1602LCD/" "" "9.991 ns" { rst lcd:inst1|clkcnt[9]~424 lcd:inst1|clkcnt[0] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "9.991 ns" { rst rst~combout lcd:inst1|clkcnt[9]~424 lcd:inst1|clkcnt[0] } { 0.000ns 0.000ns 4.828ns 1.760ns } { 0.000ns 1.132ns 0.511ns 1.760ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "lcd.v" "" { Text "E:/PLD/调试/接口实验/1602LCD/lcd.v" 99 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "mclk destination 12.533 ns - Shortest register " "Info: - Shortest clock path from clock \"mclk\" to destination register is 12.533 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns mclk 1 CLK PIN_127 4 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_127; Fanout = 4; CLK Node = 'mclk'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_v" "UNKNOWN" "V1" "E:/PLD/调试/接口实验/1602LCD/db/lcd_v.quartus_db" { Floorplan "E:/PLD/调试/接口实验/1602LCD/" "" "" { mclk } "NODE_NAME" } "" } } { "lcd_v.bdf" "" { Schematic "E:/PLD/调试/接口实验/1602LCD/lcd_v.bdf" { { 48 -96 72 64 "mclk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.273 ns) + CELL(1.294 ns) 7.699 ns div16:inst\|count\[3\] 2 REG LC_X11_Y4_N2 17 " "Info: 2: + IC(5.273 ns) + CELL(1.294 ns) = 7.699 ns; Loc. = LC_X11_Y4_N2; Fanout = 17; REG Node = 'div16:inst\|count\[3\]'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_v" "UNKNOWN" "V1" "E:/PLD/调试/接口实验/1602LCD/db/lcd_v.quartus_db" { Floorplan "E:/PLD/调试/接口实验/1602LCD/" "" "6.567 ns" { mclk div16:inst|count[3] } "NODE_NAME" } "" } } { "DIV16.v" "" { Text "E:/PLD/调试/接口实验/1602LCD/DIV16.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.916 ns) + CELL(0.918 ns) 12.533 ns lcd:inst1\|clkcnt\[0\] 3 REG LC_X13_Y6_N2 4 " "Info: 3: + IC(3.916 ns) + CELL(0.918 ns) = 12.533 ns; Loc. = LC_X13_Y6_N2; Fanout = 4; REG Node = 'lcd:inst1\|clkcnt\[0\]'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_v" "UNKNOWN" "V1" "E:/PLD/调试/接口实验/1602LCD/db/lcd_v.quartus_db" { Floorplan "E:/PLD/调试/接口实验/1602LCD/" "" "4.834 ns" { div16:inst|count[3] lcd:inst1|clkcnt[0] } "NODE_NAME" } "" } } { "lcd.v" "" { Text "E:/PLD/调试/接口实验/1602LCD/lcd.v" 99 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.344 ns ( 26.68 % ) " "Info: Total cell delay = 3.344 ns ( 26.68 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.189 ns ( 73.32 % ) " "Info: Total interconnect delay = 9.189 ns ( 73.32 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_v" "UNKNOWN" "V1" "E:/PLD/调试/接口实验/1602LCD/db/lcd_v.quartus_db" { Floorplan "E:/PLD/调试/接口实验/1602LCD/" "" "12.533 ns" { mclk div16:inst|count[3] lcd:inst1|clkcnt[0] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "12.533 ns" { mclk mclk~combout div16:inst|count[3] lcd:inst1|clkcnt[0] } { 0.000ns 0.000ns 5.273ns 3.916ns } { 0.000ns 1.132ns 1.294ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_v" "UNKNOWN" "V1" "E:/PLD/调试/接口实验/1602LCD/db/lcd_v.quartus_db" { Floorplan "E:/PLD/调试/接口实验/1602LCD/" "" "9.991 ns" { rst lcd:inst1|clkcnt[9]~424 lcd:inst1|clkcnt[0] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "9.991 ns" { rst rst~combout lcd:inst1|clkcnt[9]~424 lcd:inst1|clkcnt[0] } { 0.000ns 0.000ns 4.828ns 1.760ns } { 0.000ns 1.132ns 0.511ns 1.760ns } } } { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_v" "UNKNOWN" "V1" "E:/PLD/调试/接口实验/1602LCD/db/lcd_v.quartus_db" { Floorplan "E:/PLD/调试/接口实验/1602LCD/" "" "12.533 ns" { mclk div16:inst|count[3] lcd:inst1|clkcnt[0] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "12.533 ns" { mclk mclk~combout div16:inst|count[3] lcd:inst1|clkcnt[0] } { 0.000ns 0.000ns 5.273ns 3.916ns } { 0.000ns 1.132ns 1.294ns 0.918ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "mclk data\[3\] lcd:inst1\|data\[3\]~reg0 33.462 ns register " "Info: tco from clock \"mclk\" to destination pin \"data\[3\]\" through register \"lcd:inst1\|data\[3\]~reg0\" is 33.462 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "mclk source 28.897 ns + Longest register " "Info: + Longest clock path from clock \"mclk\" to source register is 28.897 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns mclk 1 CLK PIN_127 4 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_127; Fanout = 4; CLK Node = 'mclk'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_v" "UNKNOWN" "V1" "E:/PLD/调试/接口实验/1602LCD/db/lcd_v.quartus_db" { Floorplan "E:/PLD/调试/接口实验/1602LCD/" "" "" { mclk } "NODE_NAME" } "" } } { "lcd_v.bdf" "" { Schematic "E:/PLD/调试/接口实验/1602LCD/lcd_v.bdf" { { 48 -96 72 64 "mclk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.273 ns) + CELL(1.294 ns) 7.699 ns div16:inst\|count\[3\] 2 REG LC_X11_Y4_N2 17 " "Info: 2: + IC(5.273 ns) + CELL(1.294 ns) = 7.699 ns; Loc. = LC_X11_Y4_N2; Fanout = 17; REG Node = 'div16:inst\|count\[3\]'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_v" "UNKNOWN" "V1" "E:/PLD/调试/接口实验/1602LCD/db/lcd_v.quartus_db" { Floorplan "E:/PLD/调试/接口实验/1602LCD/" "" "6.567 ns" { mclk div16:inst|count[3] } "NODE_NAME" } "" } } { "DIV16.v" "" { Text "E:/PLD/调试/接口实验/1602LCD/DIV16.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.916 ns) + CELL(1.294 ns) 12.909 ns lcd:inst1\|clkcnt\[4\] 3 REG LC_X13_Y6_N6 4 " "Info: 3: + IC(3.916 ns) + CELL(1.294 ns) = 12.909 ns; Loc. = LC_X13_Y6_N6; Fanout = 4; REG Node = 'lcd:inst1\|clkcnt\[4\]'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_v" "UNKNOWN" "V1" "E:/PLD/调试/接口实验/1602LCD/db/lcd_v.quartus_db" { Floorplan "E:/PLD/调试/接口实验/1602LCD/" "" "5.210 ns" { div16:inst|count[3] lcd:inst1|clkcnt[4] } "NODE_NAME" } "" } } { "lcd.v" "" { Text "E:/PLD/调试/接口实验/1602LCD/lcd.v" 99 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.946 ns) + CELL(0.914 ns) 14.769 ns rtl~107 4 COMB LC_X13_Y6_N0 1 " "Info: 4: + IC(0.946 ns) + CELL(0.914 ns) = 14.769 ns; Loc. = LC_X13_Y6_N0; Fanout = 1; COMB Node = 'rtl~107'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_v" "UNKNOWN" "V1" "E:/PLD/调试/接口实验/1602LCD/db/lcd_v.quartus_db" { Floorplan "E:/PLD/调试/接口实验/1602LCD/" "" "1.860 ns" { lcd:inst1|clkcnt[4] rtl~107 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.709 ns) + CELL(0.914 ns) 17.392 ns rtl~110 5 COMB LC_X15_Y6_N2 2 " "Info: 5: + IC(1.709 ns) + CELL(0.914 ns) = 17.392 ns; Loc. = LC_X15_Y6_N2; Fanout = 2; COMB Node = 'rtl~110'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_v" "UNKNOWN" "V1" "E:/PLD/调试/接口实验/1602LCD/db/lcd_v.quartus_db" { Floorplan "E:/PLD/调试/接口实验/1602LCD/" "" "2.623 ns" { rtl~107 rtl~110 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.662 ns) + CELL(1.294 ns) 19.348 ns lcd:inst1\|clkdiv 6 REG LC_X15_Y6_N5 3 " "Info: 6: + IC(0.662 ns) + CELL(1.294 ns) = 19.348 ns; Loc. = LC_X15_Y6_N5; Fanout = 3; REG Node = 'lcd:inst1\|clkdiv'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_v" "UNKNOWN" "V1" "E:/PLD/调试/接口实验/1602LCD/db/lcd_v.quartus_db" { Floorplan "E:/PLD/调试/接口实验/1602LCD/" "" "1.956 ns" { rtl~110 lcd:inst1|clkdiv } "NODE_NAME" } "" } } { "lcd.v" "" { Text "E:/PLD/调试/接口实验/1602LCD/lcd.v" 114 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.309 ns) + CELL(1.294 ns) 24.951 ns lcd:inst1\|clk_int 7 REG LC_X12_Y3_N2 28 " "Info: 7: + IC(4.309 ns) + CELL(1.294 ns) = 24.951 ns; Loc. = LC_X12_Y3_N2; Fanout = 28; REG Node = 'lcd:inst1\|clk_int'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_v" "UNKNOWN" "V1" "E:/PLD/调试/接口实验/1602LCD/db/lcd_v.quartus_db" { Floorplan "E:/PLD/调试/接口实验/1602LCD/" "" "5.603 ns" { lcd:inst1|clkdiv lcd:inst1|clk_int } "NODE_NAME" } "" } } { "lcd.v" "" { Text "E:/PLD/调试/接口实验/1602LCD/lcd.v" 121 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.028 ns) + CELL(0.918 ns) 28.897 ns lcd:inst1\|data\[3\]~reg0 8 REG LC_X13_Y10_N8 1 " "Info: 8: + IC(3.028 ns) + CELL(0.918 ns) = 28.897 ns; Loc. = LC_X13_Y10_N8; Fanout = 1; REG Node = 'lcd:inst1\|data\[3\]~reg0'" {  } { { "d:/program files/altera/quartus51/bin/Report_Wi