lcd_v.tan.qmsg

用EPM1270实现的1602液晶驱动Verilog

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "23 " "Warning: Found 23 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "lcd:inst1\|clkcnt\[15\] " "Info: Detected ripple clock \"lcd:inst1\|clkcnt\[15\]\" as buffer" {  } { { "lcd.v" "" { Text "E:/PLD/调试/接口实验/1602LCD/lcd.v" 99 -1 0 } } { "d:/program files/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst1\|clkcnt\[15\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst1\|clkcnt\[12\] " "Info: Detected ripple clock \"lcd:inst1\|clkcnt\[12\]\" as buffer" {  } { { "lcd.v" "" { Text "E:/PLD/调试/接口实验/1602LCD/lcd.v" 99 -1 0 } } { "d:/program files/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst1\|clkcnt\[12\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst1\|clkcnt\[14\] " "Info: Detected ripple clock \"lcd:inst1\|clkcnt\[14\]\" as buffer" {  } { { "lcd.v" "" { Text "E:/PLD/调试/接口实验/1602LCD/lcd.v" 99 -1 0 } } { "d:/program files/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst1\|clkcnt\[14\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst1\|clkcnt\[13\] " "Info: Detected ripple clock \"lcd:inst1\|clkcnt\[13\]\" as buffer" {  } { { "lcd.v" "" { Text "E:/PLD/调试/接口实验/1602LCD/lcd.v" 99 -1 0 } } { "d:/program files/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst1\|clkcnt\[13\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst1\|clkcnt\[11\] " "Info: Detected ripple clock \"lcd:inst1\|clkcnt\[11\]\" as buffer" {  } { { "lcd.v" "" { Text "E:/PLD/调试/接口实验/1602LCD/lcd.v" 99 -1 0 } } { "d:/program files/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst1\|clkcnt\[11\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst1\|clkcnt\[10\] " "Info: Detected ripple clock \"lcd:inst1\|clkcnt\[10\]\" as buffer" {  } { { "lcd.v" "" { Text "E:/PLD/调试/接口实验/1602LCD/lcd.v" 99 -1 0 } } { "d:/program files/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst1\|clkcnt\[10\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst1\|clkcnt\[9\] " "Info: Detected ripple clock \"lcd:inst1\|clkcnt\[9\]\" as buffer" {  } { { "lcd.v" "" { Text "E:/PLD/调试/接口实验/1602LCD/lcd.v" 99 -1 0 } } { "d:/program files/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst1\|clkcnt\[9\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst1\|clkcnt\[8\] " "Info: Detected ripple clock \"lcd:inst1\|clkcnt\[8\]\" as buffer" {  } { { "lcd.v" "" { Text "E:/PLD/调试/接口实验/1602LCD/lcd.v" 99 -1 0 } } { "d:/program files/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst1\|clkcnt\[8\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst1\|clkcnt\[6\] " "Info: Detected ripple clock \"lcd:inst1\|clkcnt\[6\]\" as buffer" {  } { { "lcd.v" "" { Text "E:/PLD/调试/接口实验/1602LCD/lcd.v" 99 -1 0 } } { "d:/program files/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst1\|clkcnt\[6\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst1\|clkcnt\[7\] " "Info: Detected ripple clock \"lcd:inst1\|clkcnt\[7\]\" as buffer" {  } { { "lcd.v" "" { Text "E:/PLD/调试/接口实验/1602LCD/lcd.v" 99 -1 0 } } { "d:/program files/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst1\|clkcnt\[7\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst1\|clkcnt\[5\] " "Info: Detected ripple clock \"lcd:inst1\|clkcnt\[5\]\" as buffer" {  } { { "lcd.v" "" { Text "E:/PLD/调试/接口实验/1602LCD/lcd.v" 99 -1 0 } } { "d:/program files/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst1\|clkcnt\[5\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst1\|clkcnt\[4\] " "Info: Detected ripple clock \"lcd:inst1\|clkcnt\[4\]\" as buffer" {  } { { "lcd.v" "" { Text "E:/PLD/调试/接口实验/1602LCD/lcd.v" 99 -1 0 } } { "d:/program files/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst1\|clkcnt\[4\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst1\|clkcnt\[3\] " "Info: Detected ripple clock \"lcd:inst1\|clkcnt\[3\]\" as buffer" {  } { { "lcd.v" "" { Text "E:/PLD/调试/接口实验/1602LCD/lcd.v" 99 -1 0 } } { "d:/program files/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst1\|clkcnt\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst1\|clkcnt\[2\] " "Info: Detected ripple clock \"lcd:inst1\|clkcnt\[2\]\" as buffer" {  } { { "lcd.v" "" { Text "E:/PLD/调试/接口实验/1602LCD/lcd.v" 99 -1 0 } } { "d:/program files/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst1\|clkcnt\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "rtl~108 " "Info: Detected gated clock \"rtl~108\" as buffer" {  } { { "d:/program files/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "rtl~108" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "rtl~109 " "Info: Detected gated clock \"rtl~109\" as buffer" {  } { { "d:/program files/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "rtl~109" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "rtl~106 " "Info: Detected gated clock \"rtl~106\" as buffer" {  } { { "d:/program files/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "rtl~106" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "rtl~107 " "Info: Detected gated clock \"rtl~107\" as buffer" {  } { { "d:/program files/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "rtl~107" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst1\|clkcnt\[1\] " "Info: Detected ripple clock \"lcd:inst1\|clkcnt\[1\]\" as buffer" {  } { { "lcd.v" "" { Text "E:/PLD/调试/接口实验/1602LCD/lcd.v" 99 -1 0 } } { "d:/program files/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst1\|clkcnt\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "div16:inst\|count\[3\] " "Info: Detected ripple clock \"div16:inst\|count\[3\]\" as buffer" {  } { { "DIV16.v" "" { Text "E:/PLD/调试/接口实验/1602LCD/DIV16.v" 9 -1 0 } } { "d:/program files/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "div16:inst\|count\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst1\|clkcnt\[0\] " "Info: Detected ripple clock \"lcd:inst1\|clkcnt\[0\]\" as buffer" {  } { { "lcd.v" "" { Text "E:/PLD/调试/接口实验/1602LCD/lcd.v" 99 -1 0 } } { "d:/program files/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst1\|clkcnt\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst1\|clk_int " "Info: Detected ripple clock \"lcd:inst1\|clk_int\" as buffer" {  } { { "lcd.v" "" { Text "E:/PLD/调试/接口实验/1602LCD/lcd.v" 121 -1 0 } } { "d:/program files/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst1\|clk_int" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "lcd:inst1\|clkdiv " "Info: Detected ripple clock \"lcd:inst1\|clkdiv\" as buffer" {  } { { "lcd.v" "" { Text "E:/PLD/调试/接口实验/1602LCD/lcd.v" 114 -1 0 } } { "d:/program files/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "lcd:inst1\|clkdiv" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "mclk register lcd:inst1\|clkcnt\[4\] register lcd:inst1\|clkcnt\[6\] 108.5 MHz 9.217 ns Internal " "Info: Clock \"mclk\" has Internal fmax of 108.5 MHz between source register \"lcd:inst1\|clkcnt\[4\]\" and destination register \"lcd:inst1\|clkcnt\[6\]\" (period= 9.217 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.508 ns + Longest register register " "Info: + Longest register to register delay is 8.508 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lcd:inst1\|clkcnt\[4\] 1 REG LC_X13_Y6_N6 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X13_Y6_N6; Fanout = 4; REG Node = 'lcd:inst1\|clkcnt\[4\]'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_v" "UNKNOWN" "V1" "E:/PLD/调试/接口实验/1602LCD/db/lcd_v.quartus_db" { Floorplan "E:/PLD/调试/接口实验/1602LCD/" "" "" { lcd:inst1|clkcnt[4] } "NODE_NAME" } "" } } { "lcd.v" "" { Text "E:/PLD/调试/接口实验/1602LCD/lcd.v" 99 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.946 ns) + CELL(0.914 ns) 1.860 ns rtl~107 2 COMB LC_X13_Y6_N0 1 " "Info: 2: + IC(0.946 ns) + CELL(0.914 ns) = 1.860 ns; Loc. = LC_X13_Y6_N0; Fanout = 1; COMB Node = 'rtl~107'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_v" "UNKNOWN" "V1" "E:/PLD/调试/接口实验/1602LCD/db/lcd_v.quartus_db" { Floorplan "E:/PLD/调试/接口实验/1602LCD/" "" "1.860 ns" { lcd:inst1|clkcnt[4] rtl~107 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.709 ns) + CELL(0.914 ns) 4.483 ns rtl~110 3 COMB LC_X15_Y6_N2 2 " "Info: 3: + IC(1.709 ns) + CELL(0.914 ns) = 4.483 ns; Loc. = LC_X15_Y6_N2; Fanout = 2; COMB Node = 'rtl~110'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_v" "UNKNOWN" "V1" "E:/PLD/调试/接口实验/1602LCD/db/lcd_v.quartus_db" { Floorplan "E:/PLD/调试/接口实验/1602LCD/" "" "2.623 ns" { rtl~107 rtl~110 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.305 ns) + CELL(0.200 ns) 4.988 ns lcd:inst1\|clkcnt\[9\]~424 4 COMB LC_X15_Y6_N3 16 " "Info: 4: + IC(0.305 ns) + CELL(0.200 ns) = 4.988 ns; Loc. = LC_X15_Y6_N3; Fanout = 16; COMB Node = 'lcd:inst1\|clkcnt\[9\]~424'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_v" "UNKNOWN" "V1" "E:/PLD/调试/接口实验/1602LCD/db/lcd_v.quartus_db" { Floorplan "E:/PLD/调试/接口实验/1602LCD/" "" "0.505 ns" { rtl~110 lcd:inst1|clkcnt[9]~424 } "NODE_NAME" } "" } } { "lcd.v" "" { Text "E:/PLD/调试/接口实验/1602LCD/lcd.v" 99 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.760 ns) + CELL(1.760 ns) 8.508 ns lcd:inst1\|clkcnt\[6\] 5 REG LC_X13_Y6_N8 4 " "Info: 5: + IC(1.760 ns) + CELL(1.760 ns) = 8.508 ns; Loc. = LC_X13_Y6_N8; Fanout = 4; REG Node = 'lcd:inst1\|clkcnt\[6\]'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_v" "UNKNOWN" "V1" "E:/PLD/调试/接口实验/1602LCD/db/lcd_v.quartus_db" { Floorplan "E:/PLD/调试/接口实验/1602LCD/" "" "3.520 ns" { lcd:inst1|clkcnt[9]~424 lcd:inst1|clkcnt[6] } "NODE_NAME" } "" } } { "lcd.v" "" { Text "E:/PLD/调试/接口实验/1602LCD/lcd.v" 99 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.788 ns ( 44.52 % ) " "Info: Total cell delay = 3.788 ns ( 44.52 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.720 ns ( 55.48 % ) " "Info: Total interconnect delay = 4.720 ns ( 55.48 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_v" "UNKNOWN" "V1" "E:/PLD/调试/接口实验/1602LCD/db/lcd_v.quartus_db" { Floorplan "E:/PLD/调试/接口实验/1602LCD/" "" "8.508 ns" { lcd:inst1|clkcnt[4] rtl~107 rtl~110 lcd:inst1|clkcnt[9]~424 lcd:inst1|clkcnt[6] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "8.508 ns" { lcd:inst1|clkcnt[4] rtl~107 rtl~110 lcd:inst1|clkcnt[9]~424 lcd:inst1|clkcnt[6] } { 0.000ns 0.946ns 1.709ns 0.305ns 1.760ns } { 0.000ns 0.914ns 0.914ns 0.200ns 1.760ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "mclk destination 12.533 ns + Shortest register " "Info: + Shortest clock path from clock \"mclk\" to destination register is 12.533 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns mclk 1 CLK PIN_127 4 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_127; Fanout = 4; CLK Node = 'mclk'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_v" "UNKNOWN" "V1" "E:/PLD/调试/接口实验/1602LCD/db/lcd_v.quartus_db" { Floorplan "E:/PLD/调试/接口实验/1602LCD/" "" "" { mclk } "NODE_NAME" } "" } } { "lcd_v.bdf" "" { Schematic "E:/PLD/调试/接口实验/1602LCD/lcd_v.bdf" { { 48 -96 72 64 "mclk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.273 ns) + CELL(1.294 ns) 7.699 ns div16:inst\|count\[3\] 2 REG LC_X11_Y4_N2 17 " "Info: 2: + IC(5.273 ns) + CELL(1.294 ns) = 7.699 ns; Loc. = LC_X11_Y4_N2; Fanout = 17; REG Node = 'div16:inst\|count\[3\]'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_v" "UNKNOWN" "V1" "E:/PLD/调试/接口实验/1602LCD/db/lcd_v.quartus_db" { Floorplan "E:/PLD/调试/接口实验/1602LCD/" "" "6.567 ns" { mclk div16:inst|count[3] } "NODE_NAME" } "" } } { "DIV16.v" "" { Text "E:/PLD/调试/接口实验/1602LCD/DIV16.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.916 ns) + CELL(0.918 ns) 12.533 ns lcd:inst1\|clkcnt\[6\] 3 REG LC_X13_Y6_N8 4 " "Info: 3: + IC(3.916 ns) + CELL(0.918 ns) = 12.533 ns; Loc. = LC_X13_Y6_N8; Fanout = 4; REG Node = 'lcd:inst1\|clkcnt\[6\]'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_v" "UNKNOWN" "V1" "E:/PLD/调试/接口实验/1602LCD/db/lcd_v.quartus_db" { Floorplan "E:/PLD/调试/接口实验/1602LCD/" "" "4.834 ns" { div16:inst|count[3] lcd:inst1|clkcnt[6] } "NODE_NAME" } "" } } { "lcd.v" "" { Text "E:/PLD/调试/接口实验/1602LCD/lcd.v" 99 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.344 ns ( 26.68 % ) " "Info: Total cell delay = 3.344 ns ( 26.68 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.189 ns ( 73.32 % ) " "Info: Total interconnect delay = 9.189 ns ( 73.32 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_v" "UNKNOWN" "V1" "E:/PLD/调试/接口实验/1602LCD/db/lcd_v.quartus_db" { Floorplan "E:/PLD/调试/接口实验/1602LCD/" "" "12.533 ns" { mclk div16:inst|count[3] lcd:inst1|clkcnt[6] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "12.533 ns" { mclk mclk~combout div16:inst|count[3] lcd:inst1|clkcnt[6] } { 0.000ns 0.000ns 5.273ns 3.916ns } { 0.000ns 1.132ns 1.294ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "mclk source 12.533 ns - Longest register " "Info: - Longest clock path from clock \"mclk\" to source register is 12.533 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns mclk 1 CLK PIN_127 4 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_127; Fanout = 4; CLK Node = 'mclk'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_v" "UNKNOWN" "V1" "E:/PLD/调试/接口实验/1602LCD/db/lcd_v.quartus_db" { Floorplan "E:/PLD/调试/接口实验/1602LCD/" "" "" { mclk } "NODE_NAME" } "" } } { "lcd_v.bdf" "" { Schematic "E:/PLD/调试/接口实验/1602LCD/lcd_v.bdf" { { 48 -96 72 64 "mclk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.273 ns) + CELL(1.294 ns) 7.699 ns div16:inst\|count\[3\] 2 REG LC_X11_Y4_N2 17 " "Info: 2: + IC(5.273 ns) + CELL(1.294 ns) = 7.699 ns; Loc. = LC_X11_Y4_N2; Fanout = 17; REG Node = 'div16:inst\|count\[3\]'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_v" "UNKNOWN" "V1" "E:/PLD/调试/接口实验/1602LCD/db/lcd_v.quartus_db" { Floorplan "E:/PLD/调试/接口实验/1602LCD/" "" "6.567 ns" { mclk div16:inst|count[3] } "NODE_NAME" } "" } } { "DIV16.v" "" { Text "E:/PLD/调试/接口实验/1602LCD/DIV16.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.916 ns) + CELL(0.918 ns) 12.533 ns lcd:inst1\|clkcnt\[4\] 3 REG LC_X13_Y6_N6 4 " "Info: 3: + IC(3.916 ns) + CELL(0.918 ns) = 12.533 ns; Loc. = LC_X13_Y6_N6; Fanout = 4; REG Node = 'lcd:inst1\|clkcnt\[4\]'" {  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_v" "UNKNOWN" "V1" "E:/PLD/调试/接口实验/1602LCD/db/lcd_v.quartus_db" { Floorplan "E:/PLD/调试/接口实验/1602LCD/" "" "4.834 ns" { div16:inst|count[3] lcd:inst1|clkcnt[4] } "NODE_NAME" } "" } } { "lcd.v" "" { Text "E:/PLD/调试/接口实验/1602LCD/lcd.v" 99 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.344 ns ( 26.68 % ) " "Info: Total cell delay = 3.344 ns ( 26.68 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.189 ns ( 73.32 % ) " "Info: Total interconnect delay = 9.189 ns ( 73.32 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_v" "UNKNOWN" "V1" "E:/PLD/调试/接口实验/1602LCD/db/lcd_v.quartus_db" { Floorplan "E:/PLD/调试/接口实验/1602LCD/" "" "12.533 ns" { mclk div16:inst|count[3] lcd:inst1|clkcnt[4] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "12.533 ns" { mclk mclk~combout div16:inst|count[3] lcd:inst1|clkcnt[4] } { 0.000ns 0.000ns 5.273ns 3.916ns } { 0.000ns 1.132ns 1.294ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_v" "UNKNOWN" "V1" "E:/PLD/调试/接口实验/1602LCD/db/lcd_v.quartus_db" { Floorplan "E:/PLD/调试/接口实验/1602LCD/" "" "12.533 ns" { mclk div16:inst|count[3] lcd:inst1|clkcnt[6] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "12.533 ns" { mclk mclk~combout div16:inst|count[3] lcd:inst1|clkcnt[6] } { 0.000ns 0.000ns 5.273ns 3.916ns } { 0.000ns 1.132ns 1.294ns 0.918ns } } } { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_v" "UNKNOWN" "V1" "E:/PLD/调试/接口实验/1602LCD/db/lcd_v.quartus_db" { Floorplan "E:/PLD/调试/接口实验/1602LCD/" "" "12.533 ns" { mclk div16:inst|count[3] lcd:inst1|clkcnt[4] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "12.533 ns" { mclk mclk~combout div16:inst|count[3] lcd:inst1|clkcnt[4] } { 0.000ns 0.000ns 5.273ns 3.916ns } { 0.000ns 1.132ns 1.294ns 0.918ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "lcd.v" "" { Text "E:/PLD/调试/接口实验/1602LCD/lcd.v" 99 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "lcd.v" "" { Text "E:/PLD/调试/接口实验/1602LCD/lcd.v" 99 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_v" "UNKNOWN" "V1" "E:/PLD/调试/接口实验/1602LCD/db/lcd_v.quartus_db" { Floorplan "E:/PLD/调试/接口实验/1602LCD/" "" "8.508 ns" { lcd:inst1|clkcnt[4] rtl~107 rtl~110 lcd:inst1|clkcnt[9]~424 lcd:inst1|clkcnt[6] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "8.508 ns" { lcd:inst1|clkcnt[4] rtl~107 rtl~110 lcd:inst1|clkcnt[9]~424 lcd:inst1|clkcnt[6] } { 0.000ns 0.946ns 1.709ns 0.305ns 1.760ns } { 0.000ns 0.914ns 0.914ns 0.200ns 1.760ns } } } { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_v" "UNKNOWN" "V1" "E:/PLD/调试/接口实验/1602LCD/db/lcd_v.quartus_db" { Floorplan "E:/PLD/调试/接口实验/1602LCD/" "" "12.533 ns" { mclk div16:inst|count[3] lcd:inst1|clkcnt[6] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "12.533 ns" { mclk mclk~combout div16:inst|count[3] lcd:inst1|clkcnt[6] } { 0.000ns 0.000ns 5.273ns 3.916ns } { 0.000ns 1.132ns 1.294ns 0.918ns } } } { "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/program files/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "lcd_v" "UNKNOWN" "V1" "E:/PLD/调试/接口实验/1602LCD/db/lcd_v.quartus_db" { Floorplan "E:/PLD/调试/接口实验/1602LCD/" "" "12.533 ns" { mclk div16:inst|count[3] lcd:inst1|clkcnt[4] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus51/bin/Technology_Viewer.qrui" "12.533 ns" { mclk mclk~combout div16:inst|count[3] lcd:inst1|clkcnt[4] } { 0.000ns 0.000ns 5.273ns 3.916ns } { 0.000ns 1.132ns 1.294ns 0.918ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "mclk 2 " "Warning: Circuit may not operate. Detected 2 non-operational path(s) clocked by clock \"mclk\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0}