lcd_v.hier_info

用EPM1270实现的1602液晶驱动Verilog

|lcd_v
lcd_e <= lcd:inst1.lcd_e
mclk => div16:inst.clk
rst => div16:inst.rst
rst => lcd:inst1.rst
lcd_rw <= lcd:inst1.lcd_rw
lcd_rs <= lcd:inst1.lcd_rs
data[0] <= lcd:inst1.data[0]
data[1] <= lcd:inst1.data[1]
data[2] <= lcd:inst1.data[2]
data[3] <= lcd:inst1.data[3]
data[4] <= lcd:inst1.data[4]
data[5] <= lcd:inst1.data[5]
data[6] <= lcd:inst1.data[6]
data[7] <= lcd:inst1.data[7]


|lcd_v|lcd:inst1
clk => clkcnt[14].CLK
clk => clkcnt[13].CLK
clk => clkcnt[12].CLK
clk => clkcnt[11].CLK
clk => clkcnt[10].CLK
clk => clkcnt[9].CLK
clk => clkcnt[8].CLK
clk => clkcnt[7].CLK
clk => clkcnt[6].CLK
clk => clkcnt[5].CLK
clk => clkcnt[4].CLK
clk => clkcnt[3].CLK
clk => clkcnt[2].CLK
clk => clkcnt[1].CLK
clk => clkcnt[0].CLK
clk => clkcnt[15].CLK
rst => clkdiv~0.OUTPUTSELECT
rst => always4~5.IN0
rst => always4~9.IN0
rst => always4~12.IN0
rst => always4~15.IN0
rst => always4~18.IN0
rst => always4~21.IN0
rst => always4~24.IN0
rst => always4~27.IN0
rst => clk_int~0.OUTPUTSELECT
rst => lcd_e~0.OUTPUTSELECT
rst => address[5].ACLR
rst => address[4].ACLR
rst => address[3].ACLR
rst => address[2].ACLR
rst => address[1].ACLR
rst => address[0].ACLR
rst => flag.ACLR
rst => clkcnt~24.OUTPUTSELECT
rst => clkcnt~23.OUTPUTSELECT
rst => clkcnt~22.OUTPUTSELECT
rst => clkcnt~21.OUTPUTSELECT
rst => clkcnt~20.OUTPUTSELECT
rst => clkcnt~19.OUTPUTSELECT
rst => clkcnt~18.OUTPUTSELECT
rst => clkcnt~17.OUTPUTSELECT
rst => clkcnt~16.OUTPUTSELECT
rst => clkcnt~25.OUTPUTSELECT
rst => clkcnt~26.OUTPUTSELECT
rst => clkcnt~27.OUTPUTSELECT
rst => clkcnt~28.OUTPUTSELECT
rst => clkcnt~29.OUTPUTSELECT
rst => clkcnt~30.OUTPUTSELECT
rst => clkcnt~31.OUTPUTSELECT
rst => lcd_rs~reg0.ENA
rst => lcd_rw~reg0.ENA
rst => state~11.IN1
lcd_e <= lcd_e~reg0.DB_MAX_OUTPUT_PORT_TYPE
lcd_rw <= lcd_rw~reg0.DB_MAX_OUTPUT_PORT_TYPE
lcd_rs <= lcd_rs~reg0.DB_MAX_OUTPUT_PORT_TYPE
data[0] <= always4~28.DB_MAX_OUTPUT_PORT_TYPE
data[1] <= always4~26.DB_MAX_OUTPUT_PORT_TYPE
data[2] <= always4~23.DB_MAX_OUTPUT_PORT_TYPE
data[3] <= always4~20.DB_MAX_OUTPUT_PORT_TYPE
data[4] <= always4~17.DB_MAX_OUTPUT_PORT_TYPE
data[5] <= always4~14.DB_MAX_OUTPUT_PORT_TYPE
data[6] <= always4~11.DB_MAX_OUTPUT_PORT_TYPE
data[7] <= always4~8.DB_MAX_OUTPUT_PORT_TYPE


|lcd_v|div16:inst
clk => count[2].CLK
clk => count[1].CLK
clk => count[0].CLK
clk => count[3].CLK
rst => count[2].ACLR
rst => count[1].ACLR
rst => count[0].ACLR
rst => count[3].ACLR
clk_16 <= count[3].DB_MAX_OUTPUT_PORT_TYPE