lcd_v.map.qmsg

用EPM1270实现的1602液晶驱动Verilog

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Oct 13 18:41:55 2006 " "Info: Processing started: Fri Oct 13 18:41:55 2006" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off lcd_v -c lcd_v " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off lcd_v -c lcd_v" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "DIV16.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file DIV16.v" { { "Info" "ISGN_ENTITY_NAME" "1 div16 " "Info: Found entity 1: div16" {  } { { "DIV16.v" "" { Text "E:/PLD/调试/接口实验/1602LCD/DIV16.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "lcd.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file lcd.v" { { "Info" "ISGN_ENTITY_NAME" "1 lcd " "Info: Found entity 1: lcd" {  } { { "lcd.v" "" { Text "E:/PLD/调试/接口实验/1602LCD/lcd.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Warning" "WSGN_FILE_IS_MISSING" "E:/PLD/调试/接口实验/1602LCD/div200.v " "Warning: Can't analyze file -- file E:/PLD/调试/接口实验/1602LCD/div200.v is missing" {  } {  } 0 0 "Can't analyze file -- file %1!s! is missing" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "lcd_v.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file lcd_v.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 lcd_v " "Info: Found entity 1: lcd_v" {  } { { "lcd_v.bdf" "" { Schematic "E:/PLD/调试/接口实验/1602LCD/lcd_v.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "lcd_v " "Info: Elaborating entity \"lcd_v\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lcd lcd:inst1 " "Info: Elaborating entity \"lcd\" for hierarchy \"lcd:inst1\"" {  } { { "lcd_v.bdf" "inst1" { Schematic "E:/PLD/调试/接口实验/1602LCD/lcd_v.bdf" { { 104 288 400 232 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "READFLAG lcd.v(33) " "Warning (10036): Verilog HDL or VHDL warning at lcd.v(33): object \"READFLAG\" assigned a value but never read" {  } { { "lcd.v" "" { Text "E:/PLD/调试/接口实验/1602LCD/lcd.v" 33 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "READRAM lcd.v(35) " "Warning (10036): Verilog HDL or VHDL warning at lcd.v(35): object \"READRAM\" assigned a value but never read" {  } { { "lcd.v" "" { Text "E:/PLD/调试/接口实验/1602LCD/lcd.v" 35 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "cur_dec lcd.v(38) " "Warning (10036): Verilog HDL or VHDL warning at lcd.v(38): object \"cur_dec\" assigned a value but never read" {  } { { "lcd.v" "" { Text "E:/PLD/调试/接口实验/1602LCD/lcd.v" 38 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "cur_shift lcd.v(39) " "Warning (10036): Verilog HDL or VHDL warning at lcd.v(39): object \"cur_shift\" assigned a value but never read" {  } { { "lcd.v" "" { Text "E:/PLD/调试/接口实验/1602LCD/lcd.v" 39 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "shift_display lcd.v(44) " "Warning (10036): Verilog HDL or VHDL warning at lcd.v(44): object \"shift_display\" assigned a value but never read" {  } { { "lcd.v" "" { Text "E:/PLD/调试/接口实验/1602LCD/lcd.v" 44 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "right_shift lcd.v(46) " "Warning (10036): Verilog HDL or VHDL warning at lcd.v(46): object \"right_shift\" assigned a value but never read" {  } { { "lcd.v" "" { Text "E:/PLD/调试/接口实验/1602LCD/lcd.v" 46 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "datawidth4 lcd.v(49) " "Warning (10036): Verilog HDL or VHDL warning at lcd.v(49): object \"datawidth4\" assigned a value but never read" {  } { { "lcd.v" "" { Text "E:/PLD/调试/接口实验/1602LCD/lcd.v" 49 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "oneline lcd.v(51) " "Warning (10036): Verilog HDL or VHDL warning at lcd.v(51): object \"oneline\" assigned a value but never read" {  } { { "lcd.v" "" { Text "E:/PLD/调试/接口实验/1602LCD/lcd.v" 51 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "font5x7 lcd.v(53) " "Warning (10036): Verilog HDL or VHDL warning at lcd.v(53): object \"font5x7\" assigned a value but never read" {  } { { "lcd.v" "" { Text "E:/PLD/调试/接口实验/1602LCD/lcd.v" 53 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 lcd.v(107) " "Warning (10230): Verilog HDL assignment warning at lcd.v(107): truncated value with size 32 to match size of target (16)" {  } { { "lcd.v" "" { Text "E:/PLD/调试/接口实验/1602LCD/lcd.v" 107 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 lcd.v(111) " "Warning (10230): Verilog HDL assignment warning at lcd.v(111): truncated value with size 32 to match size of target (1)" {  } { { "lcd.v" "" { Text "E:/PLD/调试/接口实验/1602LCD/lcd.v" 111 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 lcd.v(157) " "Warning (10230): Verilog HDL assignment warning at lcd.v(157): truncated value with size 32 to match size of target (1)" {  } { { "lcd.v" "" { Text "E:/PLD/调试/接口实验/1602LCD/lcd.v" 157 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 lcd.v(161) " "Warning (10230): Verilog HDL assignment warning at lcd.v(161): truncated value with size 32 to match size of target (1)" {  } { { "lcd.v" "" { Text "E:/PLD/调试/接口实验/1602LCD/lcd.v" 161 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 lcd.v(163) " "Warning (10230): Verilog HDL assignment warning at lcd.v(163): truncated value with size 32 to match size of target (1)" {  } { { "lcd.v" "" { Text "E:/PLD/调试/接口实验/1602LCD/lcd.v" 163 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 lcd.v(165) " "Warning (10230): Verilog HDL assignment warning at lcd.v(165): truncated value with size 32 to match size of target (1)" {  } { { "lcd.v" "" { Text "E:/PLD/调试/接口实验/1602LCD/lcd.v" 165 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}