📄 lcd_v.fit.rpt
字号:
+---------------------------------------------------+
; Interconnect Usage Summary ;
+----------------------------+----------------------+
; Interconnect Resource Type ; Usage ;
+----------------------------+----------------------+
; C4s ; 15 / 2,870 ( < 1 % ) ;
; Direct links ; 36 / 3,938 ( < 1 % ) ;
; Global clocks ; 4 / 4 ( 100 % ) ;
; LAB clocks ; 14 / 72 ( 19 % ) ;
; LUT chains ; 4 / 1,143 ( < 1 % ) ;
; Local interconnects ; 109 / 3,938 ( 3 % ) ;
; R4s ; 52 / 2,832 ( 2 % ) ;
+----------------------------+----------------------+
+---------------------------------------------------------------------------+
; LAB Logic Elements ;
+--------------------------------------------+------------------------------+
; Number of Logic Elements (Average = 5.47) ; Number of LABs (Total = 15) ;
+--------------------------------------------+------------------------------+
; 1 ; 5 ;
; 2 ; 1 ;
; 3 ; 2 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 1 ;
; 10 ; 6 ;
+--------------------------------------------+------------------------------+
+-------------------------------------------------------------------+
; LAB-wide Signals ;
+------------------------------------+------------------------------+
; LAB-wide Signals (Average = 2.07) ; Number of LABs (Total = 15) ;
+------------------------------------+------------------------------+
; 1 Async. clear ; 7 ;
; 1 Clock ; 14 ;
; 1 Clock enable ; 6 ;
; 1 Sync. clear ; 3 ;
; 2 Clock enables ; 1 ;
+------------------------------------+------------------------------+
+----------------------------------------------------------------------------+
; LAB Signals Sourced ;
+---------------------------------------------+------------------------------+
; Number of Signals Sourced (Average = 5.67) ; Number of LABs (Total = 15) ;
+---------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 5 ;
; 2 ; 1 ;
; 3 ; 2 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 1 ;
; 10 ; 4 ;
; 11 ; 1 ;
; 12 ; 1 ;
+---------------------------------------------+------------------------------+
+--------------------------------------------------------------------------------+
; LAB Signals Sourced Out ;
+-------------------------------------------------+------------------------------+
; Number of Signals Sourced Out (Average = 3.47) ; Number of LABs (Total = 15) ;
+-------------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 6 ;
; 2 ; 4 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 1 ;
; 7 ; 0 ;
; 8 ; 4 ;
+-------------------------------------------------+------------------------------+
+----------------------------------------------------------------------------+
; LAB Distinct Inputs ;
+---------------------------------------------+------------------------------+
; Number of Distinct Inputs (Average = 6.40) ; Number of LABs (Total = 15) ;
+---------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 4 ;
; 3 ; 3 ;
; 4 ; 0 ;
; 5 ; 2 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 1 ;
; 9 ; 0 ;
; 10 ; 0 ;
; 11 ; 1 ;
; 12 ; 2 ;
; 13 ; 2 ;
+---------------------------------------------+------------------------------+
+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
Info: Processing started: Fri Oct 13 18:42:04 2006
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off lcd_v -c lcd_v
Info: Selected device EPM1270T144C5 for design "lcd_v"
Info: Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
Info: Device EPM570T144C5 is compatible
Info: Device EPM570T144I5 is compatible
Info: Device EPM1270T144I5 is compatible
Info: Device EPM1270T144C5ES is compatible
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
Info: Assuming a global fmax requirement of 1000 MHz
Info: Assuming a global tsu requirement of 2.0 ns
Info: Assuming a global tco requirement of 1.0 ns
Info: Assuming a global tpd requirement of 1.0 ns
Info: Performing register packing on registers with non-logic cell location assignments
Info: Completed register packing on registers with non-logic cell location assignments
Info: Completed User Assigned Global Signals Promotion Operation
Info: Automatically promoted some destinations of signal "lcd:inst1|clk_int" to use Global clock
Info: Destination "lcd:inst1|clk_int" may be non-global or may not use global clock
Info: Automatically promoted some destinations of signal "div16:inst|count[3]" to use Global clock
Info: Destination "div16:inst|count[3]" may be non-global or may not use global clock
Info: Automatically promoted signal "mclk" to use Global clock
Info: Pin "mclk" drives global clock, but is not placed in a dedicated clock pin position
Info: Automatically promoted some destinations of signal "lcd:inst1|clkdiv" to use Global clock
Info: Destination "lcd:inst1|clkdiv" may be non-global or may not use global clock
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Moving registers into LUTs to improve timing and density
Info: Started processing fast register assignments
Info: Finished processing fast register assignments
Info: Finished moving registers into LUTs
Info: Finished register packing
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:02
Info: Estimated most critical path is register to pin delay of 4.013 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X11_Y10; Fanout = 8; REG Node = 'lcd:inst1|always4~2'
Info: 2: + IC(2.409 ns) + CELL(1.604 ns) = 4.013 ns; Loc. = PIN_109; Fanout = 0; PIN Node = 'data[0]'
Info: Total cell delay = 1.604 ns ( 39.97 % )
Info: Total interconnect delay = 2.409 ns ( 60.03 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 1%
Info: Fitter routing operations ending: elapsed time is 00:00:01
Warning: Following 1 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results
Info: Pin lcd_rw has GND driving its datain port
Info: Quartus II Fitter was successful. 0 errors, 1 warning
Info: Processing ended: Fri Oct 13 18:42:10 2006
Info: Elapsed time: 00:00:07
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