lcd_v.map.rpt

用EPM1270实现的1602液晶驱动Verilog

; state.WRITERAM     ; 0               ; 0           ; 0              ; 1          ; 1              ; 0              ; 0                 ; 0           ; 0                ; 0             ; 0                  ;
; state.SETCGRAM     ; 0               ; 0           ; 0              ; 1          ; 0              ; 1              ; 0                 ; 0           ; 0                ; 0             ; 0                  ;
; state.SWITCHMODE   ; 0               ; 0           ; 0              ; 1          ; 0              ; 0              ; 0                 ; 0           ; 1                ; 0             ; 0                  ;
; state.RETURNCURSOR ; 0               ; 0           ; 0              ; 1          ; 0              ; 0              ; 0                 ; 0           ; 0                ; 0             ; 1                  ;
; state.SETDDRAM     ; 0               ; 0           ; 1              ; 1          ; 0              ; 0              ; 0                 ; 0           ; 0                ; 0             ; 0                  ;
; state.CLEAR        ; 0               ; 1           ; 0              ; 1          ; 0              ; 0              ; 0                 ; 0           ; 0                ; 0             ; 0                  ;
; state.SETMODE      ; 0               ; 0           ; 0              ; 1          ; 0              ; 0              ; 0                 ; 0           ; 0                ; 1             ; 0                  ;
; state.SHIFT        ; 0               ; 0           ; 0              ; 1          ; 0              ; 0              ; 0                 ; 1           ; 0                ; 0             ; 0                  ;
; state.SETFUNCTION  ; 0               ; 0           ; 0              ; 1          ; 0              ; 0              ; 1                 ; 0           ; 0                ; 0             ; 0                  ;
; state.SETDDRAM1    ; 1               ; 0           ; 0              ; 1          ; 0              ; 0              ; 0                 ; 0           ; 0                ; 0             ; 0                  ;
+--------------------+-----------------+-------------+----------------+------------+----------------+----------------+-------------------+-------------+------------------+---------------+--------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 50    ;
; Number of registers using Synchronous Clear  ; 17    ;
; Number of registers using Synchronous Load   ; 1     ;
; Number of registers using Asynchronous Clear ; 20    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 15    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                            ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output  ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------+
; 3:1                ; 16 bits   ; 32 LEs        ; 16 LEs               ; 16 LEs                 ; Yes        ; |lcd_v|lcd:inst1|clkcnt[9]  ;
; 4:1                ; 6 bits    ; 12 LEs        ; 6 LEs                ; 6 LEs                  ; Yes        ; |lcd_v|lcd:inst1|address[0] ;
; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; No         ; |lcd_v|lcd:inst1|state~4    ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------+


+--------------------------------------------------------+
; Parameter Settings for User Entity Instance: lcd:inst1 ;
+----------------+-------------+-------------------------+
; Parameter Name ; Value       ; Type                    ;
+----------------+-------------+-------------------------+
; IDLE           ; 00000000000 ; Binary                  ;
; CLEAR          ; 00000000001 ; Binary                  ;
; RETURNCURSOR   ; 00000000010 ; Binary                  ;
; SETMODE        ; 00000000100 ; Binary                  ;
; SWITCHMODE     ; 00000001000 ; Binary                  ;
; SHIFT          ; 00000010000 ; Binary                  ;
; SETFUNCTION    ; 00000100000 ; Binary                  ;
; SETCGRAM       ; 00001000000 ; Binary                  ;
; SETDDRAM       ; 00010000000 ; Binary                  ;
; SETDDRAM1      ; 00010000001 ; Binary                  ;
; READFLAG       ; 00100000000 ; Binary                  ;
; WRITERAM       ; 01000000000 ; Binary                  ;
; READRAM        ; 10000000000 ; Binary                  ;
; cur_inc        ; 1           ; Untyped                 ;
; cur_dec        ; 0           ; Untyped                 ;
; cur_shift      ; 1           ; Untyped                 ;
; cur_noshift    ; 0           ; Untyped                 ;
; open_display   ; 1           ; Untyped                 ;
; open_cur       ; 0           ; Untyped                 ;
; blank_cur      ; 0           ; Untyped                 ;
; shift_display  ; 1           ; Untyped                 ;
; shift_cur      ; 0           ; Untyped                 ;
; right_shift    ; 1           ; Untyped                 ;
; left_shift     ; 0           ; Untyped                 ;
; datawidth8     ; 1           ; Untyped                 ;
; datawidth4     ; 0           ; Untyped                 ;
; twoline        ; 1           ; Untyped                 ;
; oneline        ; 0           ; Untyped                 ;
; font5x10       ; 1           ; Untyped                 ;
; font5x7        ; 0           ; Untyped                 ;
+----------------+-------------+-------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/PLD/调试/接口实验/1602LCD/lcd_v.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Fri Oct 13 18:41:55 2006
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off lcd_v -c lcd_v
Info: Found 1 design units, including 1 entities, in source file DIV16.v
    Info: Found entity 1: div16
Info: Found 1 design units, including 1 entities, in source file lcd.v
    Info: Found entity 1: lcd
Warning: Can't analyze file -- file E:/PLD/调试/接口实验/1602LCD/div200.v is missing
Info: Found 1 design units, including 1 entities, in source file lcd_v.bdf
    Info: Found entity 1: lcd_v
Info: Elaborating entity "lcd_v" for the top level hierarchy
Info: Elaborating entity "lcd" for hierarchy "lcd:inst1"
Warning (10036): Verilog HDL or VHDL warning at lcd.v(33): object "READFLAG" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at lcd.v(35): object "READRAM" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at lcd.v(38): object "cur_dec" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at lcd.v(39): object "cur_shift" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at lcd.v(44): object "shift_display" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at lcd.v(46): object "right_shift" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at lcd.v(49): object "datawidth4" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at lcd.v(51): object "oneline" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at lcd.v(53): object "font5x7" assigned a value but never read
Warning (10230): Verilog HDL assignment warning at lcd.v(107): truncated value with size 32 to match size of target (16)
Warning (10230): Verilog HDL assignment warning at lcd.v(111): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at lcd.v(157): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at lcd.v(161): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at lcd.v(163): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at lcd.v(165): truncated value with size 32 to match size of target (1)
Warning (10270): Verilog HDL statement warning at lcd.v(58): incomplete Case Statement has no default case item
Warning (10241): Verilog HDL Function Declaration warning at lcd.v(55): function "ddram" may return a Don't Care value because its output register may not be assigned a value in every possible path through the function
Warning (10230): Verilog HDL assignment warning at lcd.v(176): truncated value with size 32 to match size of target (6)
Warning (10230): Verilog HDL assignment warning at lcd.v(194): truncated value with size 32 to match size of target (6)
Warning (10030): Tied undriven net "ddram[7]" at lcd.v(55) to 0
Warning (10030): Tied undriven net "ddram[6]" at lcd.v(55) to 0
Warning (10030): Tied undriven net "ddram[5]" at lcd.v(55) to 0
Warning (10030): Tied undriven net "ddram[4]" at lcd.v(55) to 0
Warning (10030): Tied undriven net "ddram[3]" at lcd.v(55) to 0
Warning (10030): Tied undriven net "ddram[2]" at lcd.v(55) to 0
Warning (10030): Tied undriven net "ddram[1]" at lcd.v(55) to 0
Warning (10030): Tied undriven net "ddram[0]" at lcd.v(55) to 0
Info: Elaborating entity "div16" for hierarchy "div16:inst"
Warning (10230): Verilog HDL assignment warning at DIV16.v(12): truncated value with size 32 to match size of target (4)
Info: Duplicate registers merged to single register
    Info: Duplicate register "lcd:inst1|always4~25" merged to single register "lcd:inst1|always4~2"
    Info: Duplicate register "lcd:inst1|always4~22" merged to single register "lcd:inst1|always4~2"
    Info: Duplicate register "lcd:inst1|always4~19" merged to single register "lcd:inst1|always4~2"
    Info: Duplicate register "lcd:inst1|always4~16" merged to single register "lcd:inst1|always4~2"
    Info: Duplicate register "lcd:inst1|always4~13" merged to single register "lcd:inst1|always4~2"
    Info: Duplicate register "lcd:inst1|always4~10" merged to single register "lcd:inst1|always4~2"
    Info: Duplicate register "lcd:inst1|always4~7" merged to single register "lcd:inst1|always4~2"
Warning: Reduced register "lcd:inst1|lcd_rw" with stuck data_in port to stuck value GND
Info: State machine "|lcd_v|lcd:inst1|state" contains 11 states
Info: Selected Auto state machine encoding method for state machine "|lcd_v|lcd:inst1|state"
Info: Encoding result for state machine "|lcd_v|lcd:inst1|state"
    Info: Completed encoding using 11 state bits
        Info: Encoded state bit "lcd:inst1|state.SETDDRAM1"
        Info: Encoded state bit "lcd:inst1|state.CLEAR"
        Info: Encoded state bit "lcd:inst1|state.SETDDRAM"
        Info: Encoded state bit "lcd:inst1|state.IDLE"
        Info: Encoded state bit "lcd:inst1|state.WRITERAM"
        Info: Encoded state bit "lcd:inst1|state.SETCGRAM"
        Info: Encoded state bit "lcd:inst1|state.SETFUNCTION"
        Info: Encoded state bit "lcd:inst1|state.SHIFT"
        Info: Encoded state bit "lcd:inst1|state.SWITCHMODE"
        Info: Encoded state bit "lcd:inst1|state.SETMODE"
        Info: Encoded state bit "lcd:inst1|state.RETURNCURSOR"
    Info: State "|lcd_v|lcd:inst1|state.IDLE" uses code string "00000000000"
    Info: State "|lcd_v|lcd:inst1|state.WRITERAM" uses code string "00011000000"
    Info: State "|lcd_v|lcd:inst1|state.SETCGRAM" uses code string "00010100000"
    Info: State "|lcd_v|lcd:inst1|state.SWITCHMODE" uses code string "00010000100"
    Info: State "|lcd_v|lcd:inst1|state.RETURNCURSOR" uses code string "00010000001"
    Info: State "|lcd_v|lcd:inst1|state.SETDDRAM" uses code string "00110000000"
    Info: State "|lcd_v|lcd:inst1|state.CLEAR" uses code string "01010000000"
    Info: State "|lcd_v|lcd:inst1|state.SETMODE" uses code string "00010000010"
    Info: State "|lcd_v|lcd:inst1|state.SHIFT" uses code string "00010001000"
    Info: State "|lcd_v|lcd:inst1|state.SETFUNCTION" uses code string "00010010000"
    Info: State "|lcd_v|lcd:inst1|state.SETDDRAM1" uses code string "10010000000"
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "lcd_rw" stuck at GND
Info: Implemented 99 device resources after synthesis - the final resource count might be different
    Info: Implemented 2 input pins
    Info: Implemented 11 output pins
    Info: Implemented 86 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 32 warnings
    Info: Processing ended: Fri Oct 13 18:42:01 2006
    Info: Elapsed time: 00:00:07