📄 dsasm_functions.cpp
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lstrcat((*Disasm)->Opcode,m_Bytes);
return; // exit the function
}
// XCHG Register
if(Op>=0x91 && Op<=0x97)
{
m_Opcode=(*(*Opcode+Pos)); // 1 byte Opcode
m_Opcode+=0x30; // Add 0x30 in order to get values of EAX-EDI (trick)
IndexAdd=0; // Dont Add to the index counter.
m_OpcodeSize=1; // 1 byte opcode
}
// (->) / reg8
if(d==0 && w==0)
{
RM=REG8;
reg1=(m_Opcode&0x07);
reg2=(m_Opcode&0x38)>>3;
}
// (->) / reg32
if(d==0 && w==1)
{
RM=REG32;
if(PrefixReg==1)
RM=REG16; // (->) / reg16 (RegPerfix is being used)
reg1=(m_Opcode&0x07);
reg2=(m_Opcode&0x38)>>3;
}
// (<-) / reg8
if(d==1 && w==0)
{
RM=REG8;
reg2=(m_Opcode&0x07);
reg1=(m_Opcode&0x38)>>3;
}
// (<-) / reg32
if(d==1 && w==1)
{
RM=REG32;
if(PrefixReg==1)
RM=REG16; // (<-) / reg16
reg2=(m_Opcode&0x07);
reg1=(m_Opcode&0x38)>>3;
}
// Check Opcode Size (XCHG changes it)
if(m_OpcodeSize==1)
{
wsprintf(temp,"%02X",Op);
}
else // Default
{
SwapWord((BYTE*)(*Opcode+Pos),&wOp,&wMem);
wsprintf(temp,"%04X",wOp);
}
switch(Op)
{
case 0x6B: // IMUL REG,REG,IIM
{
SwapWord((BYTE*)(*Opcode+Pos+1),&wOp,&wMem);
FOpcode=wOp&0x00FF;
if(FOpcode>0x7F) // check for signed numbers!!
{
FOpcode = 0x100-FOpcode; // -XX (Signed)
wsprintf(temp,"%s",Scale[0]); // '-' aritmathic (Signed)
}
else
strcpy(temp,"");
m_OpcodeSize=3;
(*(*index))++;
wsprintf(assembly,"imul %s,%s,%s%02X",regs[RM][reg1],regs[RM][reg2],temp,FOpcode);
wsprintf(temp,"%02X%04X",Op,wOp);
}
break;
case 0x8F: // POP REG
{
if((BYTE)(*(*Opcode+Pos+1))>=0xC8) // above bytes has !=000 there for invalid
lstrcat((*Disasm)->Remarks,"Invalid Instruction");
wsprintf(assembly,"%s %s",instruction,regs[RM][reg2]);
}
break;
case 0xD0: case 0xD1:
{
wsprintf(assembly,"%s %s, 1",ArtimaticInstructions[REG],regs[RM][reg1]);
}
break;
case 0xD2: case 0xD3:
{
wsprintf(assembly,"%s %s, cl",ArtimaticInstructions[REG],regs[RM][reg2]);
}
break;
case 0xD8:// FPU Instruction
{
if(REG==3) // fcomp uses 1 operand
{
wsprintf(assembly,"%s %s",FpuInstructions[REG],FpuRegs[reg1]);
}
else // st(0) is the dest
{
wsprintf(assembly,"%s st,%s",FpuInstructions[REG],FpuRegs[reg1]);
}
}
break;
case 0xD9: // FPU Instructions
{
// 2 byte FPU Instructions
switch((BYTE)(*(*Opcode+Pos+1)))
{
case 0xC8:case 0xC9:case 0xCA:case 0xCB:
case 0xCC:case 0xCD:case 0xCE:case 0xCF:
{
wsprintf(assembly,"fxch %s",FpuRegs[reg1]);
}
break;
case 0xD1:case 0xD2:case 0xD3:case 0xD4:
case 0xD5:case 0xD6:case 0xD7:
{
wsprintf(assembly,"fst %s",FpuRegs[reg1]);
}
break;
case 0xD8:case 0xD9:case 0xDA:case 0xDB:
case 0xDC:case 0xDD:case 0xDE:case 0xDF:
{
wsprintf(assembly,"fstp %s",FpuRegs[reg1]);
}
break;
case 0xE2:case 0xE3:case 0xE6:case 0xE7:
{
wsprintf(assembly,"fldenv %s",FpuRegs[reg1]);
}
break;
case 0xEF:
{
wsprintf(assembly,"fldcw %s",FpuRegs[reg1]);
}
break;
case 0xC0:case 0xC1:case 0xC2:case 0xC3:case 0xC4:
case 0xC5:case 0xC6:case 0xC7:
{
wsprintf(assembly,"fld %s",FpuRegs[reg1]);
}
break;
case 0xD0: strcpy(assembly,"fnop"); break;
case 0xE0: strcpy(assembly,"fchs"); break;
case 0xE1: strcpy(assembly,"fabs"); break;
case 0xE4: strcpy(assembly,"ftst"); break;
case 0xE5: strcpy(assembly,"fxam"); break;
case 0xE8: strcpy(assembly,"fld1"); break;
case 0xE9: strcpy(assembly,"fldl2t"); break;
case 0xEA: strcpy(assembly,"fldl2e"); break;
case 0xEB: strcpy(assembly,"fldpi"); break;
case 0xEC: strcpy(assembly,"fldlg2"); break;
case 0xED: strcpy(assembly,"fldln2"); break;
case 0xEE: strcpy(assembly,"fldz"); break;
case 0xF0: strcpy(assembly,"f2xm1"); break;
case 0xF1: strcpy(assembly,"fyl2x"); break;
case 0xF2: strcpy(assembly,"fptan"); break;
case 0xF3: strcpy(assembly,"fpatan"); break;
case 0xF4: strcpy(assembly,"fxtract"); break;
case 0xF5: strcpy(assembly,"fprem1"); break;
case 0xF6: strcpy(assembly,"fdecstp"); break;
case 0xF7: strcpy(assembly,"fincstp"); break;
case 0xF8: strcpy(assembly,"fprem"); break;
case 0xF9: strcpy(assembly,"fyl2xp1"); break;
case 0xFA: strcpy(assembly,"fsqrt"); break;
case 0xFB: strcpy(assembly,"fsincos"); break;
case 0xFC: strcpy(assembly,"frndint"); break;
case 0xFD: strcpy(assembly,"fscale"); break;
case 0xFE: strcpy(assembly,"fsin"); break;
case 0xFF: strcpy(assembly,"fcos"); break;
}
}
break;
case 0xDA: // FPU Instructions
{
switch((BYTE)(*(*Opcode+Pos+1)))
{
case 0xC0:case 0xC1:case 0xC2:case 0xC3: // FCMOVB
case 0xC4:case 0xC5:case 0xC6:case 0xC7:
{
wsprintf(assembly,"fcmovb st,%s",FpuRegs[reg2]);
}
break;
case 0xC8:case 0xC9:case 0xCA:case 0xCB: // FCMOVE
case 0xCC:case 0xCD:case 0xCE:case 0xCF:
{
wsprintf(assembly,"fcmove st,%s",FpuRegs[reg2]);
}
break;
case 0xD0:case 0xD1:case 0xD2:case 0xD3: // FCMOVBE
case 0xD4:case 0xD5:case 0xD6:case 0xD7:
{
wsprintf(assembly,"fcmovbe st,%s",FpuRegs[reg2]);
}
break;
case 0xD8:case 0xD9:case 0xDA:case 0xDB: // FCMOVU
case 0xDC:case 0xDD:case 0xDE:case 0xDF:
{
wsprintf(assembly,"fcmovu st,%s",FpuRegs[reg2]);
}
break;
// Default Signed FPU Instructions
default: wsprintf(assembly,"%s %s",FpuInstructionsSigned[REG],FpuRegs[reg2]); break;
}
}
break;
case 0xDB: // FPU Instruction
{
switch((BYTE)(*(*Opcode+Pos+1)))
{
case 0xC0:case 0xC1:case 0xC2:case 0xC3: // FCMOVNB
case 0xC4:case 0xC5:case 0xC6:case 0xC7: // FCMOVNB
{
wsprintf(assembly,"fcmovnb st,%s",FpuRegs[reg2]);
}
break;
case 0xC8:case 0xC9:case 0xCA:case 0xCB: // FCMOVNE
case 0xCC:case 0xCD:case 0xCE:case 0xCF: // FCMOVNE
{
wsprintf(assembly,"fcmovne st,%s",FpuRegs[reg2]);
}
break;
case 0xD0:case 0xD1:case 0xD2:case 0xD3: // FCMOVNBE
case 0xD4:case 0xD5:case 0xD6:case 0xD7: // FCMOVNBE
{
wsprintf(assembly,"fcmovnbe st,%s",FpuRegs[reg2]);
}
break;
case 0xD8:case 0xD9:case 0xDA:case 0xDB: // FCMOVNU
case 0xDC:case 0xDD:case 0xDE:case 0xDF: // FCMOVNU
{
wsprintf(assembly,"fcmovnu st,%s",FpuRegs[reg2]);
}
break;
case 0xE0: strcpy(assembly,"feni"); break;
case 0xE1: strcpy(assembly,"fdisi"); break;
case 0xE2: strcpy(assembly,"fclex"); break;
case 0xE3: strcpy(assembly,"finit"); break;
case 0xE4: case 0xE5: case 0xE6: case 0xE7: // (Invalid) Reserved instructions..???
{
lstrcat((*Disasm)->Remarks,"Invalid Instruction");
strcpy(assembly,"???");
}
break;
case 0xE8:case 0xE9:case 0xEA:case 0xEB: //
case 0xEC:case 0xED:case 0xEE:case 0xEF: //
{
wsprintf(assembly,"fucomi st,%s",FpuRegs[reg2]);
}
break;
case 0xF0:case 0xF1:case 0xF2:case 0xF3: //
case 0xF4:case 0xF5:case 0xF6:case 0xF7: //
{
wsprintf(assembly,"fcomi st,%s",FpuRegs[reg2]);
}
break;
default: wsprintf(assembly,"fstp %s",FpuRegs[reg2]); break;
}
}
break;
case 0xDC:// FPU Instruction
{
if(REG==3) // fcomp uses 1 operand
{
wsprintf(assembly,"%s %s",FpuInstructions[REG],FpuRegs[reg1]);
}
else // st(0) is the src
{
switch(REG) // fdiv<->fdivr / fsub <-> fsubr (changed positions)
{
case 4:REG++;break;
case 5:REG--;break;
case 6:REG++;break;
case 7:REG--;break;
}
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