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📄 clk60.fit

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💻 FIT
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-- MAX+plus II Compiler Fit File      
-- Version 10.2 07/10/2002            
-- Compiled: 09/18/2008 21:56:58      

-- Copyright (C) 1988-2002 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera.  Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner.  Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors.  No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.

CHIP "clk60"
BEGIN

    DEVICE = "EPM7032SLC44-5";

    "clk"                          : INPUT_PIN  = 43     ;
    "clr"                          : INPUT_PIN  = 1      ;
    "h1"                           : OUTPUT_PIN = 18     ; -- LC13
    "h2"                           : OUTPUT_PIN = 12     ; -- LC8
    "h3"                           : OUTPUT_PIN = 16     ; -- LC11
    "h4"                           : OUTPUT_PIN = 17     ; -- LC12
    "h5"                           : OUTPUT_PIN = 4      ; -- LC1
    "m0"                           : OUTPUT_PIN = 37     ; -- LC21
    "m1"                           : OUTPUT_PIN = 39     ; -- LC19
    "m2"                           : OUTPUT_PIN = 34     ; -- LC23
    "m3"                           : OUTPUT_PIN = 40     ; -- LC18
    "m4"                           : OUTPUT_PIN = 41     ; -- LC17
    "m5"                           : OUTPUT_PIN = 36     ; -- LC22
    "m6"                           : OUTPUT_PIN = 27     ; -- LC29
    "s0"                           : OUTPUT_PIN = 5      ; -- LC2
    "s1"                           : OUTPUT_PIN = 29     ; -- LC27
    "s2"                           : OUTPUT_PIN = 33     ; -- LC24
    "s3"                           : OUTPUT_PIN = 31     ; -- LC26
    "s4"                           : OUTPUT_PIN = 28     ; -- LC28
    "s5"                           : OUTPUT_PIN = 26     ; -- LC30
    "s6"                           : OUTPUT_PIN = 25     ; -- LC31

END;

INTERNAL_INFO "clk60"
BEGIN
	DEVICE = EPM7032SLC44-5;
	LC31    : LORAX = "G57R0,PA28R0C1";
	LC30    : LORAX = "G56R0,PA30R0C1";
	LC28    : LORAX = "G41R0,PA20R0C1";
	LC26    : LORAX = "G39R0,PA21R0C1";
	LC24    : LORAX = "G33R0,PA10R0C1";
	LC27    : LORAX = "G40R0,PA19R0C1";
	LC2     : LORAX = "G10R0,PA1R0C1";
	LC29    : LORAX = "G55R0,PA27R0C1";
	LC22    : LORAX = "G31R0,PA14R0C1,PA14R0C0";
	LC17    : LORAX = "G13R0,PA7R0C1,PA7R0C0";
	LC18    : LORAX = "G14R0,PA5R0C1,PA5R0C0";
	LC23    : LORAX = "G32R0,PA12R0C1";
	LC19    : LORAX = "G15R0,PA3R0C1,PA3R0C0";
	LC21    : LORAX = "G30R0,PA16R0C1,PA16R0C0";
	LC1     : LORAX = "G9R0,PA2R0C0";
	LC12    : LORAX = "G37R0,PA26R0C0";
	LC11    : LORAX = "G36R0,PA23R0C0";
	LC8     : LORAX = "G29R0,PA9R0C0";
	LC13    : LORAX = "G51R0,PA29R0C0";
END;

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