pulserate.lst

测量脉搏的源码 Cypress公司使用 CY27443 完成相关的功能

        0668: 0D 39    ADC   [X+57],A
        066A: 03 3A    ADD   A,[X+58]
        066C: 07 FF 61 ADD   [X-1],97
        066F: 62 63 64 MOV   REG[99],100
        0672: 65 66    ASL   [ADC_iResult+1]
        0674: 00       SSC   
        0675: BE 10    JNZ   0x0486
        0677: 00       SSC   
        0678: 00       SSC   
        0679: 00       SSC   
        067A: 00       SSC   
        067B: 00       SSC   
        067C: 00       SSC   
        067D: FE 00    INDEX 0x047F
        067F: 00       SSC   
        0680: 00       SSC   
        0681: 00       SSC   
        0682: 00       SSC   
        0683: 00       SSC   
        0684: 00       SSC   
        0685: 00       SSC   
        0686: 00       SSC   
        0687: 00       SSC   
        0688: 00       SSC   
        0689: 00       SSC   
        068A: 00       SSC   
        068B: 01 2C    ADD   A,44
        068D: 00       SSC   
        068E: 00       SSC   
        068F: 00       SSC   
        0690: 00       SSC   
        0691: 00       SSC   
        0692: 00       SSC   
        0693: 00       SSC   
        0694: 00       SSC   
FILE: lib\psocconfig.asm
(0001) ; Generated by PSoC Designer ver 4.1 BETA b923 : 11 December, 2003
(0002) ;
(0003) ;
(0004) ;  PSoCConfig.asm
(0005) ;
(0006) ;  Version 0.84
(0007) ;  Data: 19 December, 2000
(0008) ;  Copyright Cypress MicroSystems 2000
(0009) ;
(0010) ;  This file is generated by the Device Editor on Application Generation.
(0011) ;  It contains code which loads the configuration data table generated in
(0012) ;  the file PSoCConfigTBL.asm
(0013) ;  
(0014) ;  DO NOT EDIT THIS FILE MANUALLY, AS IT IS OVERWRITTEN!!!
(0015) ;  Edits to this file will not be preserved.
(0016) ;
(0017) include "m8c.inc"
(0018) include "GlobalParams.inc"
(0019) 
(0020) export LoadConfigInit
(0021) export _LoadConfigInit
(0022) export LoadConfig_pulserate
(0023) export _LoadConfig_pulserate
(0024) 
(0025) export NO_SHADOW
(0026) export _NO_SHADOW
(0027) 
(0028) FLAG_CFG_MASK:		equ	10h			;M8C flag register REG address bit mask
(0029) END_CONFIG_TABLE:	equ	ffh			;end of config table indicator	
(0030) 
(0031) AREA psoc_config(rom, rel)
(0032) 
(0033) _LoadConfigInit:
(0034)  LoadConfigInit:
(0035) 	
(0036) 	lcall	LoadConfigTBL_pulserate_Ordered
        0695: 7C 04 F5 LCALL 0x04F5
(0037) 	lcall	LoadConfig_pulserate
        0698: 7C 06 9C LCALL 0x069C
(0038) 
(0039) 	ret
        069B: 7F       RET   
(0040) 
(0041) ;
(0042) ; Load Configuration pulserate
(0043) ;
(0044) _LoadConfig_pulserate:
(0045)  LoadConfig_pulserate:
(0046)     push    a
        069C: 08       PUSH  A
(0047)     push    x
        069D: 10       PUSH  X
(0048) 	M8C_SetBank0									;switch to bank 0
        069E: 70 EF    AND   F,239
(0049) 	mov		a, 0
        06A0: 50 00    MOV   A,0
(0050) 	asr		a
        06A2: 67       ASR   A
(0051) 	mov		A, >LoadConfigTBL_pulserate_Bank0	;load bank 0 table
        06A3: 50 05    MOV   A,5
(0052) 	mov		X, <LoadConfigTBL_pulserate_Bank0
        06A5: 57 A4    MOV   X,164
(0053) 	lcall	LoadConfig								;load the bank 0 values
        06A7: 7C 06 BB LCALL 0x06BB
(0054) 	M8C_SetBank1									;set for bank 1
        06AA: 71 10    OR    F,16
(0055) 	mov		a, 1
        06AC: 50 01    MOV   A,1
(0056) 	asr		a
        06AE: 67       ASR   A
(0057) 	mov		A, >LoadConfigTBL_pulserate_Bank1	;load bank 1 table
        06AF: 50 06    MOV   A,6
(0058) 	mov		X, <LoadConfigTBL_pulserate_Bank1
        06B1: 57 21    MOV   X,33
(0059) 	lcall	LoadConfig								;load the bank 1 values
        06B3: 7C 06 BB LCALL 0x06BB
(0060) 	M8C_SetBank0									;switch to bank 0
        06B6: 70 EF    AND   F,239
(0061)     pop     x
        06B8: 20       POP   X
(0062)     pop     a
        06B9: 18       POP   A
(0063) 	ret
        06BA: 7F       RET   
(0064) 
(0065) 
(0066) ;
(0067) ; LoadConfig
(0068) ;
(0069) ;  This function is not exported.  It assumes that the address of the table
(0070) ;  to be loaded is contained in the X and A registers as if a romx instruction
(0071) ;  is the next instruction to be executed, i.e. lower address in X and uppper
(0072) ;  address in A.  There is no return value.
(0073) ;
(0074) LoadConfig:
(0075) 	add		SP, 2					;set up temp vars
        06BB: 38 02    ADD   SP,2
(0076) 	push	X
        06BD: 10       PUSH  X
(0077) 	push	A
        06BE: 08       PUSH  A
(0078) 	mov		X, SP
        06BF: 4F       MOV   X,SP
(0079) 	mov		[X-4], 0
        06C0: 56 FC 00 MOV   [X-4],0
(0080) 	jnc		LoadBank0Setup
        06C3: D0 04    JNC   0x06C8
(0081) 	mov		[X-4], 1
        06C5: 56 FC 01 MOV   [X-4],1
(0082) LoadBank0Setup:
(0083) 	pop		A
        06C8: 18       POP   A
(0084) 	pop		X
        06C9: 20       POP   X
(0085) LoadConfigLp:
(0086) 	push	X						;save config table address on stack
        06CA: 10       PUSH  X
(0087) 	push	A
        06CB: 08       PUSH  A
(0088) 	M8C_SetBank0					;switch to bank 0
        06CC: 70 EF    AND   F,239
(0089) 	M8C_ClearWDT					;clear the watchdog for long inits
        06CE: 62 E3 00 MOV   REG[227],0
(0090) 	mov		X, SP					;check for bank 1 load
        06D1: 4F       MOV   X,SP
(0091) 	tst		[X-4], 1
        06D2: 48 FC 01 TST   [X-4],1
(0092) 	jz		LoadingBank0
        06D5: A0 03    JZ    0x06D9
(0093) 	M8C_SetBank1
        06D7: 71 10    OR    F,16
(0094) LoadingBank0:
(0095) 	pop		A
        06D9: 18       POP   A
(0096) 	pop		X
        06DA: 20       POP   X
(0097) 	push	X
        06DB: 10       PUSH  X
(0098) 	push	A
        06DC: 08       PUSH  A
(0099) 	romx							;load config address
        06DD: 28       ROMX  
(0100) 	cmp		A, END_CONFIG_TABLE		;check for end of table
        06DE: 39 FF    CMP   A,255
(0101) 	jz		EndLoadConfig			;if so, end of load
        06E0: A0 1A    JZ    0x06FB
(0102) 	mov		X, SP					;save the address away
        06E2: 4F       MOV   X,SP
(0103) 	mov		[X-3], A
        06E3: 54 FD    MOV   [X-3],A
(0104) 	pop		A						;retrieve the table address
        06E5: 18       POP   A
(0105) 	pop		X
        06E6: 20       POP   X
(0106) 	inc		X						;advance to the data byte
        06E7: 75       INC   X
(0107) 	jnc		NoOverFlow1				;check for overflow
        06E8: D0 02    JNC   0x06EB
(0108) 	inc		A						;if so, increment MSB
        06EA: 74       INC   A
(0109) NoOverFlow1:	
(0110) 	push	X						;save the config table address again
        06EB: 10       PUSH  X
(0111) 	push	A
        06EC: 08       PUSH  A
(0112) 	romx							;load the config data
        06ED: 28       ROMX  
(0113) 	mov		X, SP					;retrieve the config address
        06EE: 4F       MOV   X,SP
(0114) 	mov		X, [X-3]
        06EF: 59 FD    MOV   X,[X-3]
(0115) 	mov		reg[X], A				;write the config data
        06F1: 61 00    MOV   REG[X+0],A
(0116) 	pop		A						;retrieve the table address
        06F3: 18       POP   A
(0117) 	pop		X
        06F4: 20       POP   X
(0118) 	inc		X						;advance to the next address
        06F5: 75       INC   X
(0119) 	jnc		NoOverFlow2				;check for overflow
        06F6: D0 02    JNC   0x06F9
(0120) 	inc		A						;if so, increment MSB
        06F8: 74       INC   A
(0121) NoOverFlow2:	
(0122) 	jmp		LoadConfigLp			;loop back
        06F9: 8F D0    JMP   0x06CA
(0123) EndLoadConfig:
(0124) 	pop		A						;clean up the stack
        06FB: 18       POP   A
(0125) 	pop		X
        06FC: 20       POP   X
(0126) 	add		SP, -2
        06FD: 38 FE    ADD   SP,254
(0127) 	ret
        06FF: 7F       RET   
FILE: lib\tx_serial.asm
(0001) ;;*****************************************************************************
(0002) ;;*****************************************************************************
(0003) ;;  FILENAME: TX_SERIAL.asm
(0004) ;;   Version: 2.2, Updated on 2003/11/18 at 15:02:31
(0005) ;;  Generated by PSoC Designer ver 4.1 BETA b923 : 11 December, 2003
(0006) ;;
(0007) ;;  DESCRIPTION: TX8 User Module software implementation file
(0008) ;;               for 22/24/25/26/27xxx PSoc family of devices.
(0009) ;;
(0010) ;;  NOTE: User Module APIs conform to the fastcall convention for marshalling
(0011) ;;        arguments and observe the associated "Registers are volatile" policy.
(0012) ;;        This means it is the caller's responsibility to preserve any values
(0013) ;;        in the X and A registers that are still needed after the API
(0014) ;;        function returns. Even though these registers may be preserved now,
(0015) ;;        there is no guarantee they will be preserved in future releases.
(0016) ;;-----------------------------------------------------------------------------
(0017) ;;  Copyright (c) Cypress MicroSystems 2000-2003. All Rights Reserved.
(0018) ;;*****************************************************************************
(0019) ;;*****************************************************************************
(0020) 
(0021) ;-----------------------------------------------
(0022) ; include instance specific register definitions
(0023) ;-----------------------------------------------
(0024) include "m8c.inc"
(0025) include "TX_SERIAL.inc"
(0026) 
(0027) area UserModules (ROM, REL)
(0028) ;-----------------------------------------------
(0029) ;  Global Symbols
(0030) ;-----------------------------------------------
(0031) export   TX_SERIAL_EnableInt
(0032) export  _TX_SERIAL_EnableInt
(0033) export   TX_SERIAL_DisableInt
(0034) export  _TX_SERIAL_DisableInt
(0035) export   TX_SERIAL_Start
(0036) export  _TX_SERIAL_Start
(0037) export   TX_SERIAL_Stop
(0038) export  _TX_SERIAL_Stop
(0039) export   TX_SERIAL_SendData
(0040) export  _TX_SERIAL_SendData
(0041) export   TX_SERIAL_bReadTxStatus
(0042) export  _TX_SERIAL_bReadTxStatus
(0043) 
(0044) // Old labels, will be removed in future release
(0045) // Do Not Use.
(0046) export   bTX_SERIAL_ReadTxStatus
(0047) export  _bTX_SERIAL_ReadTxStatus
(0048) 
(0049) ;-----------------------------------------------
(0050) ;  EQUATES
(0051) ;-----------------------------------------------
(0052) bfCONTROL_REG_START_BIT:   equ   1     ; Control register start bit
(0053) 
(0054) AREA UserModules (ROM, REL)
(0055) 
(0056) .SECTION
(0057) ;-----------------------------------------------------------------------------
(0058) ;  FUNCTION NAME: TX_SERIAL_EnableInt
(0059) ;
(0060) ;  DESCRIPTION:
(0061) ;     Enables this Transmitter's interrupt by setting the interrupt enable mask
(0062) ;     bit associated with this User Module. Remember to call the global interrupt
(0063) ;     enable function by using the macro: M8C_EnableGInt.
(0064) ;
(0065) ;-----------------------------------------------------------------------------
(0066) ;
(0067) ;  ARGUMENTS: none
(0068) ;
(0069) ;  RETURNS: none
(0070) ;
(0071) ;  SIDE EFFECTS:
(0072) ;    REGISTERS ARE VOLATILE:  A AND X REGISTERS MAY BE MODIFIED!
(0073) ;
(0074) ;  THEORY of OPERATION or PROCEDURE:
(0075) ;     Sets the specific user module interrupt enable mask bit.
(0076) ;
(0077) ;-----------------------------------------------------------------------------
(0078)  TX_SERIAL_EnableInt:
(0079) _TX_SERIAL_EnableInt:
(0080)    M8C_EnableIntMask  TX_SERIAL_INT_REG, TX_SERIAL_bINT_MASK
        0700: 43 E1 40 OR    REG[225],64
(0081)    ret
        0703: 7F       RET   
(0082) .ENDSECTION
(0083) 
(0084) .SECTION
(0085) ;-----------------------------------------------------------------------------
(0086) ;  FUNCTION NAME: TX_SERIAL_DisableInt
(0087) ;
(0088) ;  DESCRIPTION:
(0089) ;     Disables this TX8's interrupt by clearing the interrupt enable mask bit
(0090) ;     associated with this User Module.
(0091) ;
(0092) ;-----------------------------------------------------------------------------
(0093) ;
(0094) ;  ARGUMENTS:  none
(0095) ;
(0096) ;  RETURNS:  none
(0097) ;
(0098) ;  SIDE EFFECTS:
(0099) ;    REGISTERS ARE VOLATILE:  A AND X REGISTERS MAY BE MODIFIED!
(0100) ;
(0101) ;  THEORY of OPERATION or PROCEDURE:
(0102) ;     Clears the specific user mod