📄 pulserate.lst
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(0230) IF (PLL_MODE)
(0231) M8C_SetBank1
(0232) mov reg[OSC_CR0],(SELECT_32K_JUST | PLL_MODE_JUST | OSC_CR0_SLEEP_64Hz | OSC_CR0_CPU_3MHz)
(0233) M8C_SetBank0
(0234) M8C_ClearWDTAndSleep ; Reset the sleep timer
(0235)
(0236) mov reg[INT_VC],0 ; Clear all pending interrupts
(0237) .WaitFor16ms:
(0238) tst reg[INT_CLR0],INT_MSK0_SLEEP ; test the Interrupt Status
(0239) jz .WaitFor16ms ; TimeOut occurs on Sleep Timer 16ms
(0240) IF (WAIT_FOR_32K)
(0241) ELSE ;!(WAIT_FOR_32K)
(0242) ERROR_PSoC Disabling WAIT_FOR_32K requires that the PLL_Lock must be enabled in user code.
(0243) ENDIF ;(WAIT_FOR_32K)
(0244) ENDIF ;(PLL_MODE)
(0245)
(0246) ;-------------------------------------------------------------------------
(0247) ; Set CT block RTopMux to OUT and RBotMux to AGND. This closes leakage
(0248) ; paths through the CT blocks.
(0249) ;-------------------------------------------------------------------------
(0250) mov reg[ACB00CR0],05h
009B: 62 71 05 MOV REG[113],5
(0251) mov reg[ACB01CR0],05h
009E: 62 75 05 MOV REG[117],5
(0252) mov reg[ACB02CR0],05h
00A1: 62 79 05 MOV REG[121],5
(0253) mov reg[ACB03CR0],05h
00A4: 62 7D 05 MOV REG[125],5
(0254)
(0255) ;-------------------------------------------------------------------------
(0256) ; All the user selections and UserModule selections are now loaded,
(0257) ; except CPU frequency (CPU is runing at 12 MHz). Load the PSoC
(0258) ; configuration with a 12 MHz CPU clock to keep config time short.
(0259) ;-------------------------------------------------------------------------
(0260) lcall LoadConfigInit ; Configure PSoC blocks per Dev Editor
00A7: 7C 06 95 LCALL 0x0695
(0261)
(0262)
(0263) IF (C_LANGUAGE_SUPPORT)
(0264) call InitCRunTime ; Initialize for C language
00AA: 90 19 CALL 0x00C5
(0265) ENDIF ;(C_LANGUAGE_SUPPORT)
(0266)
(0267)
(0268) IF (SUPPLY_VOLTAGE)
(0269) ;-------------------------------------------------------------------------
(0270) ; Nominal 5.0 V operating voltage is selected.
(0271) ; Set the Precision Power-On Reset (PPOR) level for the operating voltage
(0272) ; range selected. In addition, if the SMP is running make sure time was
(0273) ; given to let Vdd slew up to the set voltage before enabling the reset.
(0274) ;-------------------------------------------------------------------------
(0275)
(0276) IF (SWITCH_MODE_PUMP ^ 1)
(0277) ;-------------------------------------------------------------------------
(0278) ; If using the SMP at 5V, must wait for Vdd to slew from 3.1V to 5V
(0279) ; The sleep interrupt will be used for timing Xtal and PLL startup.
(0280) ;-------------------------------------------------------------------------
(0281) or reg[INT_MSK0],INT_MSK0_SLEEP
(0282)
(0283) M8C_SetBank1
(0284) and reg[OSC_CR0],~OSC_CR0_SLEEP
(0285) or reg[OSC_CR0],OSC_CR0_SLEEP_512Hz
(0286) M8C_SetBank0
(0287)
(0288) M8C_ClearWDTAndSleep ; Reset the sleep timer
(0289)
(0290) mov reg[INT_VC],0 ; Clear all pending interrupts
(0291) .WaitFor2ms:
(0292) tst reg[INT_CLR0],INT_MSK0_SLEEP ; test the Interrupt Status
(0293) jz .WaitFor2ms ; TimeOut occurs on Sleep Timer 2ms
(0294) ENDIF ;(SWITCH_MODE_PUMP ^ 1)
(0295)
(0296) IF (CPU_CLOCK_JUST ^ OSC_CR0_CPU_24MHz) ; Clock is not 24MHz
(0297) ;-------------------------------------------------------------------------
(0298) ; <24 MHz operation is requested, so set PPOR to 3.0V. If a PPOR level
(0299) ; of 4.5V is desired, then VLT_CR can be set in user code.
(0300) ;-------------------------------------------------------------------------
(0301) M8C_SetBank1
(0302) and reg[VLT_CR],~VLT_CR_PORLEV
(0303) or reg[VLT_CR],VLT_CR_3V0_POR
(0304) M8C_SetBank0
(0305)
(0306) ELSE ;!(CPU_CLOCK_JUST ^ OSC_CR0_CPU_24MHz)
(0307) ;-------------------------------------------------------------------------
(0308) ; 24 MHz operation, so Vdd >= 4.75V required.
(0309) ;-------------------------------------------------------------------------
(0310) M8C_SetBank1
(0311) and reg[VLT_CR],~VLT_CR_PORLEV
(0312) or reg[VLT_CR],VLT_CR_4V75_POR
(0313) M8C_SetBank0
(0314) ENDIF ;(CPU_CLOCK_JUST ^ OSC_CR0_CPU_24MHz)
(0315)
(0316) ELSE ;!(SUPPLY_VOLTAGE)
(0317) ;-------------------------------------------------------------------------
(0318) ; Nominal 3.3 V operating voltage is selected, set the PPOR to 3.0V.
(0319) ;-------------------------------------------------------------------------
(0320) M8C_SetBank1
00AC: 71 10 OR F,16
(0321) and reg[VLT_CR],~VLT_CR_PORLEV
00AE: 41 E3 CF AND REG[227],207
(0322) // or reg[VLT_CR],VLT_CR_3V0_POR ; not needed, 0b00 is 3.0V
(0323) M8C_SetBank0
00B1: 70 EF AND F,239
(0324)
(0325) ENDIF ;(SUPPLY_VOLTAGE)
(0326)
(0327) ;-------------------------------------------------------------------------
(0328) ; Disable the Sleep interrupt that was used for timing above. In fact,
(0329) ; no interrupts should be enabled now, so may as well clear the register.
(0330) ;-------------------------------------------------------------------------
(0331) mov reg[INT_MSK0],0
00B3: 62 E0 00 MOV REG[224],0
(0332)
(0333) ;-------------------------------------------------------------------------
(0334) ; Everything has started OK. Now select requested CPU & sleep frequency.
(0335) ;-------------------------------------------------------------------------
(0336) M8C_SetBank1
00B6: 71 10 OR F,16
(0337) mov reg[OSC_CR0],(SELECT_32K_JUST | PLL_MODE_JUST | SLEEP_TIMER_JUST | CPU_CLOCK_JUST)
00B8: 62 E0 0A MOV REG[224],10
(0338) M8C_SetBank0
00BB: 70 EF AND F,239
(0339)
(0340) ;-------------------------------------------------------------------------
(0341) ; Global Interrupt are NOT enabled, this should be done in main().
(0342) ; LVD is set but will not occur unless Global Interrupts are enabled.
(0343) ; Global Interrupts should be as soon as possible in main().
(0344) ;-------------------------------------------------------------------------
(0345) mov reg[INT_VC],0 ; Clear any pending interrupts which may
00BD: 62 E2 00 MOV REG[226],0
(0346) ; have been set during the boot process.
(0347) lcall _main ; Call main
00C0: 7C 19 1A LCALL _main
(0348)
(0349) __Exit:
(0350) jmp __Exit ; Wait here till power is turned off
00C3: 8F FF JMP 0x00C3
(0351)
(0352)
(0353)
(0354) ;-----------------------------------------------------------------------------
(0355) ; C Runtime Environment Initialization
(0356) ; The following code is conditionally assembled.
(0357) ;-----------------------------------------------------------------------------
(0358)
(0359) IF (C_LANGUAGE_SUPPORT)
(0360)
(0361) InitCRunTime:
(0362) ;-----------------------------
(0363) ; clear bss segment
(0364) ;-----------------------------
(0365) mov A,0
00C5: 50 00 MOV A,0
(0366) mov [__r0],<__bss_start
00C7: 55 28 29 MOV [__r0],41
(0367) BssLoop:
(0368) cmp [__r0],<__bss_end
00CA: 3C 28 69 CMP [__r0],105
(0369) jz BssDone
00CD: A0 05 JZ 0x00D3
(0370) mvi [__r0],A
00CF: 3F 28 MVI [__r0],A
(0371) jmp BssLoop
00D1: 8F F8 JMP 0x00CA
(0372) BssDone:
(0373) ;----------------------------
(0374) ; copy idata to data segment
(0375) ;----------------------------
(0376) mov A,>__idata_start
00D3: 50 06 MOV A,6
(0377) mov X,<__idata_start
00D5: 57 75 MOV X,117
(0378) mov [__r0],<__data_start
00D7: 55 28 00 MOV [__r0],0
(0379) IDataLoop:
(0380) cmp [__r0],<__data_end
00DA: 3C 28 20 CMP [__r0],32
(0381) jz IDataDone
00DD: A0 0B JZ 0x00E9
(0382) push A
00DF: 08 PUSH A
(0383) romx
00E0: 28 ROMX
(0384) mvi [__r0],A
00E1: 3F 28 MVI [__r0],A
(0385) pop A
00E3: 18 POP A
(0386) inc X
00E4: 75 INC X
(0387) adc A,0
00E5: 09 00 ADC A,0
(0388) jmp IDataLoop
00E7: 8F F2 JMP 0x00DA
(0389) IDataDone:
(0390) ret
00E9: 7F RET
00EA: 30 HALT
00EB: 30 HALT
00EC: 30 HALT
00ED: 30 HALT
00EE: 30 HALT
00EF: 30 HALT
00F0: 30 HALT
00F1: 30 HALT
00F2: 30 HALT
00F3: 30 HALT
00F4: 30 HALT
00F5: 30 HALT
00F6: 30 HALT
00F7: 30 HALT
00F8: 30 HALT
00F9: 30 HALT
00FA: 30 HALT
00FB: 30 HALT
00FC: 30 HALT
00FD: 30 HALT
00FE: 30 HALT
00FF: 30 HALT
0100: 30 HALT
0101: 30 HALT
0102: 30 HALT
0103: 30 HALT
0104: 30 HALT
0105: 30 HALT
0106: 30 HALT
0107: 30 HALT
0108: 30 HALT
0109: 30 HALT
010A: 30 HALT
010B: 30 HALT
010C: 30 HALT
010D: 30 HALT
010E: 30 HALT
010F: 30 HALT
0110: 00 SSC
0111: 00 SSC
0112: 00 SSC
0113: 00 SSC
0114: 00 SSC
0115: 00 SSC
0116: 00 SSC
0117: 2F 00 00 OR [X+0],0
011A: 00 SSC
011B: 07 00 07 ADD [X+0],7
011E: 00 SSC
011F: 14 7F SUB [127],A
0121: 14 7F SUB [127],A
0123: 14 24 SUB [__r6],A
0125: 2A 7F OR A,[127]
0127: 2A 12 OR A,[18]
0129: C4 C8 JC 0x05F2
012B: 10 PUSH X
012C: 26 46 36 AND [_tx_buffer+3],54
012F: 49 55 22 TST REG[85],34
0132: 50 00 MOV A,0
0134: 05 03 ADD [X+3],A
0136: 00 SSC
0137: 00 SSC
0138: 00 SSC
0139: 1C 22 SBB [__rX],A
013B: 41 00 00 AND REG[0],0
013E: 41 22 1C AND REG[34],28
0141: 00 SSC
0142: 14 08 SUB [8],A
0144: 3E 08 MVI A,[8]
0146: 14 08 SUB [8],A
0148: 08 PUSH A
0149: 3E 08 MVI A,[8]
014B: 08 PUSH A
014C: 00 SSC
014D: 00 SSC
014E: 50 30 MOV A,48
0150: 00 SSC
0151: 10 PUSH X
0152: 10 PUSH X
0153: 10 PUSH X
0154: 10 PUSH X
0155: 10 PUSH X
0156: 00 SSC
0157: 60 60 MOV REG[96],A
0159: 00 SSC
015A: 00 SSC
015B: 20 POP X
015C: 10 PUSH X
015D: 08 PUSH A
015E: 04 02 ADD [2],A
0160: 3E 51 MVI A,[81]
0162: 49 45 3E TST REG[69],62
0165: 00 SSC
0166: 42 7F 40 AND REG[X+127],64
0169: 00 SSC
016A: 42 61 51 AND REG[X+97],81
016D: 49 46 21 TST REG[70],33
0170: 41 45 4B AND REG[69],75
0173: 31 18 XOR A,24
0175: 14 12 SUB [18],A
0177: 7F RET
0178: 10 PUSH X
0179: 27 45 45 AND [X+69],69
017C: 45 39 3C XOR REG[57],60
017F: 4A 49 49 TST REG[X+73],73
0182: 30 HALT
0183: 01 71 ADD A,113
0185: 09 05 ADC A,5
0187: 03 36 ADD A,[X+54]
0189: 49 49 49 TST REG[73],73
018C: 36 06 49 XOR [6],73
018F: 49 29 1E TST REG[41],30
0192: 00 SSC
0193: 36 36 00 XOR [54],0
0196: 00 SSC
0197: 00 SSC
0198: 56 36 00 MOV [X+54],0
019B: 00 SSC
019C: 08 PUSH A
019D: 14 22 SUB [__rX],A
019F: 41 00 14 AND REG[0],20
01A2: 14 14 SUB [20],A
01A4: 14 14 SUB [20],A
01A6: 00 SSC
01A7: 41 22 14 AND REG[34],20
01AA: 08 PUSH A
01AB: 02 01 ADD A,[1]
01AD: 51 09 MOV A,[9]
01AF: 06 32 49 ADD [50],73
01B2: 59 51 MOV X,[X+81]
01B4: 3E 7E MVI A,[126]
01B6: 11 11 SUB A,17
01B8: 11 7E SUB A,126
01BA: 7F RET
01BB: 49 49 49 TST REG[73],73
01BE: 36 3E 41 XOR [62],65
01C1: 41 41 22 AND REG[65],34
01C4: 7F RET
01C5: 41 41 22 AND REG[65],34
01C8: 1C 7F SBB [127],A
01CA: 49 49 49 TST REG[73],73
01CD: 41 7F 09 AND REG[127],9
01D0: 09 09 ADC A,9
01D2: 01 3E ADD A,62
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