📄 pulserate.lst
字号:
0000: 7D 00 68 LJMP 0x0068
0003: 30 HALT
FILE: .\boot.asm
(0001) ; Generated by PSoC Designer ver 4.1 BETA b923 : 11 December, 2003
(0002) ;
(0003) ;@Id: boot.tpl#46 @
(0004) ;=============================================================================
(0005) ; FILENAME: boot.asm
(0006) ; VERSION: 4.04
(0007) ; DATE: 18 November 2003
(0008) ;
(0009) ; DESCRIPTION:
(0010) ; M8C Boot Code for CY8C27xxx microcontroller family.
(0011) ;
(0012) ; Copyright (C) Cypress MicroSystems 2001-2003. All rights reserved.
(0013) ;
(0014) ; NOTES:
(0015) ; PSoC Designer's Device Editor uses a template file, BOOT.TPL, located in
(0016) ; the project's root directory to create BOOT.ASM. Any changes made to
(0017) ; BOOT.ASM will be overwritten every time the project is generated; therfore
(0018) ; changes should be made to BOOT.TPL not BOOT.ASM. Care must be taken when
(0019) ; modifying BOOT.TPL so that replacement strings (such as @PROJECT_NAME)
(0020) ; are not accidentally modified.
(0021) ;
(0022) ;=============================================================================
(0023)
(0024) include ".\lib\GlobalParams.inc"
(0025) include "m8c.inc"
(0026) include "m8ssc.inc"
(0027)
(0028) ;-----------------------------------------------------------------------------
(0029) ; Optimization flags
(0030) ;-----------------------------------------------------------------------------
(0031) C_LANGUAGE_SUPPORT: equ 1 ;Set to 0 to optimize for ASM only
(0032)
(0033) ;-----------------------------------------------------------------------------
(0034) ; The following equate is required for proper operation. Reseting its value
(0035) ; is discouraged. WAIT_FOR_32K is effective only if the crystal oscillator is
(0036) ; selected. If the designer chooses to not wait then the ECO and PLL_Lock
(0037) ; processes must take place within user code. See the family data sheet for
(0038) ; the requirements of starting the ECO and PLL lock mode.
(0039) ;-----------------------------------------------------------------------------
(0040) WAIT_FOR_32K: equ 1 ; Wait for Crystal to start before allowing main()
(0041)
(0042) ;-----------------------------------------------------------------------------
(0043) ; Export Declarations
(0044) ;-----------------------------------------------------------------------------
(0045)
(0046) export __Start
(0047) export __Exit
(0048) export __bss_start
(0049)
(0050) export __lit_start
(0051) export __idata_start
(0052) export __data_start
(0053) export __func_lit_start
(0054) export __text_start
(0055) export __usermodules_start
(0056) export __psoc_config_start
(0057)
(0058) ;-----------------------------------------------------------------------------
(0059) ; Interrupt Vector Table
(0060) ;-----------------------------------------------------------------------------
(0061) ;
(0062) ; Interrupt vector table entries are 4 bytes long and contain the code that
(0063) ; services the interrupt (or causes it to be serviced).
(0064) ;
(0065) ;-----------------------------------------------------------------------------
(0066)
(0067) AREA TOP(ROM,ABS,CON)
(0068)
(0069) org 0 ;Reset Interrupt Vector
(0070) ljmp __Start ;First instruction executed following a Reset
(0071)
(0072) org 04h ;Supply Monitor Interrupt Vector
(0073) halt ;Stop execution if power falls too low
0004: 30 HALT
0005: 30 HALT
0006: 30 HALT
0007: 30 HALT
(0074)
(0075) org 08h ;Analog Column 0 Interrupt Vector
(0076) // call void_handler
(0077) reti
0008: 7E RETI
0009: 30 HALT
000A: 30 HALT
000B: 30 HALT
(0078)
(0079) org 0Ch ;Analog Column 1 Interrupt Vector
(0080) // call void_handler
(0081) reti
000C: 7E RETI
000D: 30 HALT
000E: 30 HALT
000F: 30 HALT
(0082)
(0083) org 10h ;Analog Column 2 Interrupt Vector
(0084) // call void_handler
(0085) reti
0010: 7E RETI
0011: 30 HALT
0012: 30 HALT
0013: 30 HALT
(0086)
(0087) org 14h ;Analog Column 3 Interrupt Vector
(0088) // call void_handler
(0089) reti
0014: 7E RETI
0015: 30 HALT
0016: 30 HALT
0017: 30 HALT
(0090)
(0091) org 18h ;VC3 Interrupt Vector
(0092) // call void_handler
(0093) reti
0018: 7E RETI
0019: 30 HALT
001A: 30 HALT
001B: 30 HALT
(0094)
(0095) org 1Ch ;GPIO Interrupt Vector
(0096) // call void_handler
(0097) reti
001C: 7E RETI
001D: 30 HALT
001E: 30 HALT
001F: 30 HALT
(0098)
(0099) org 20h ;PSoC Block DBB00 Interrupt Vector
(0100) ljmp _Carrier_Timer_ISR
0020: 7D 07 F3 LJMP 0x07F3
(0101) reti
0023: 7E RETI
(0102)
(0103) org 24h ;PSoC Block DBB01 Interrupt Vector
(0104) // call void_handler
(0105) reti
0024: 7E RETI
0025: 30 HALT
0026: 30 HALT
0027: 30 HALT
(0106)
(0107) org 28h ;PSoC Block DCB02 Interrupt Vector
(0108) ljmp _ADC_PWM16_ISR
0028: 7D 08 91 LJMP 0x0891
(0109) reti
002B: 7E RETI
(0110)
(0111) org 2Ch ;PSoC Block DCB03 Interrupt Vector
(0112) ljmp _ADC_CNT_ISR
002C: 7D 08 8E LJMP 0x088E
(0113) reti
002F: 7E RETI
(0114)
(0115) org 30h ;PSoC Block DBB10 Interrupt Vector
(0116) // call void_handler
(0117) reti
0030: 7E RETI
0031: 30 HALT
0032: 30 HALT
0033: 30 HALT
(0118)
(0119) org 34h ;PSoC Block DBB11 Interrupt Vector
(0120) ljmp _Baud_ISR
0034: 7D 08 39 LJMP 0x0839
(0121) reti
0037: 7E RETI
(0122)
(0123) org 38h ;PSoC Block DCB12 Interrupt Vector
(0124) ;ljmp _TX_SERIAL_ISR
(0125) ljmp _TX_SERIAL_handler
0038: 7D 14 FB LJMP _TX_SERIAL_handler
003B: 30 HALT
(0126) ;reti
(0127)
(0128) org 3Ch ;PSoC Block DCB13 Interrupt Vector
(0129) ljmp _SPIM_ISR
003C: 7D 07 17 LJMP 0x0717
(0130) reti
003F: 7E RETI
0040: 30 HALT
0041: 30 HALT
0042: 30 HALT
0043: 30 HALT
0044: 30 HALT
0045: 30 HALT
0046: 30 HALT
0047: 30 HALT
0048: 30 HALT
0049: 30 HALT
004A: 30 HALT
004B: 30 HALT
004C: 30 HALT
004D: 30 HALT
004E: 30 HALT
004F: 30 HALT
0050: 30 HALT
0051: 30 HALT
0052: 30 HALT
0053: 30 HALT
0054: 30 HALT
0055: 30 HALT
0056: 30 HALT
0057: 30 HALT
0058: 30 HALT
0059: 30 HALT
005A: 30 HALT
005B: 30 HALT
005C: 30 HALT
005D: 30 HALT
005E: 30 HALT
005F: 30 HALT
(0131)
(0132) // 40h through 5Fh are reserved for future products
(0133)
(0134) org 60h ;PSoC I2C Interrupt Vector
(0135) ;// call void_handler
(0136) ljmp _adc_sig_proc
0060: 7D 1A A7 LJMP _adc_sig_proc
0063: 30 HALT
(0137) ;reti
(0138)
(0139) org 64h ;Sleep Timer Interrupt Vector
(0140) ;// call void_handler
(0141) ljmp _SleepTimer_handler
0064: 7D 09 9E LJMP _SleepTimer_handler
0067: 30 HALT
(0142) ;reti
(0143)
(0144) ;-----------------------------------------------------------------------------
(0145) ; Start of Execution
(0146) ; CPU is operating at 3 MHz, change to 12 MHz
(0147) ; IO Bank is Bank0
(0148) ;-----------------------------------------------------------------------------
(0149) org 68h
(0150) __Start:
(0151) IF (WATCHDOG_ENABLE)
(0152) M8C_EnableWatchDog ;Enable the WDT if selected in Global Params
(0153) ENDIF
(0154) IF (SELECT_32K)
(0155) or reg[CPU_SCR1],CPU_SCR1_ECO_ALLOWED ;ECO will be used in this project
(0156) ELSE
(0157) and reg[CPU_SCR1],~CPU_SCR1_ECO_ALLOWED ;Prevent ECO from being enabled
0068: 41 FE FB AND REG[254],251
(0158) ENDIF
(0159) ;-------------------------------------------------------------------------
(0160) ; Set the AGND Bypass bit. This is found in the BandGap Trim register, so
(0161) ; the trim value must be read from the Trim Table. That is all that is
(0162) ; done for 5V operation if the AGND Bypass pin is chosen. For 3.3V
(0163) ; operation the IMO Clock and BandGap trim registers always have to be set
(0164) ; (they default to 5V trims).
(0165) ;-------------------------------------------------------------------------
(0166) IF (SUPPLY_VOLTAGE) ; 1 means 5.0V
(0167) IF (AGND_BYPASS) ; need to set the AGNDBYP bit in BDG_TR
(0168) mov [bSSC_TABLE_TableId],1 ; Point to the Trim table
(0169) SSC_Action TABLE_READ ; Perform a table read supervisor call
(0170) M8C_SetBank1
(0171) mov A,[VOLTAGE_TRIM_5V] ; Get the bandgap trim seting for 5V
(0172) or A,AGND_BYPASS_JUST ; OR in the bypass setting
(0173) mov reg[BDG_TR],A ; Update the register value
(0174) M8C_SetBank0
(0175) ENDIF
(0176) ELSE ; 0 means 3.3V
(0177) mov [bSSC_TABLE_TableId],1 ; Point to the Trim table
006B: 55 FA 01 MOV [250],1
006E: 4F MOV X,SP
006F: 5B MOV A,X
0070: 01 03 ADD A,3
0072: 53 F9 MOV [249],A
0074: 55 F8 3A MOV [248],58
0077: 50 06 MOV A,6
(0178) SSC_Action TABLE_READ ; Perform a table read supervisor call
0079: 00 SSC
(0179) M8C_SetBank1
007A: 71 10 OR F,16
(0180) mov A,[OSCILLATOR_TRIM_3V]
007C: 51 F9 MOV A,[249]
(0181) mov reg[IMO_TR],A ; Load the 3V trim oscillator setting
007E: 60 E8 MOV REG[232],A
(0182) mov A,[VOLTAGE_TRIM_3V]
0080: 51 F8 MOV A,[248]
(0183) or A,AGND_BYPASS_JUST ; OR in the bypass setting
0082: 29 40 OR A,64
(0184) mov reg[BDG_TR],A ; Load the bandgap trim setting for 3V
0084: 60 EA MOV REG[234],A
(0185) M8C_SetBank0
0086: 70 EF AND F,239
(0186) ENDIF ;(SUPPLY_VOLTAGE)
(0187)
(0188) mov [bSSC_KEY1],0 ; Lockout Flash and Supervisiory operations
0088: 55 F8 00 MOV [248],0
(0189) mov [bSSC_KEYSP],0
008B: 55 F9 00 MOV [249],0
(0190)
(0191) mov A,_stack_start ; Set top of stack to end of used RAM
008E: 50 69 MOV A,105
(0192) swap SP,A
0090: 4E SWAP SP,A
(0193)
(0194) ;-------------------------------------------------------------------------
(0195) ; If the user has requested the Crystal oscillator then turn it on and
(0196) ; wait for it to stabilize and the system to switch over to it. The wait
(0197) ; will be one sleep timer period, approximately 1 second.
(0198) ;-------------------------------------------------------------------------
(0199)
(0200) IF (SELECT_32K & WAIT_FOR_32K)
(0201) ; Start the ECO and and leave the PLL off
(0202) ; Set SleepTimer to 1 sec to time the wait for the ECO to stabilize
(0203) M8C_SetBank1
(0204) mov reg[OSC_CR0],(SELECT_32K_JUST | OSC_CR0_SLEEP_1Hz | OSC_CR0_CPU_12MHz)
(0205) M8C_SetBank0
(0206) M8C_ClearWDTAndSleep ; Reset the sleep timer to get a full second
(0207)
(0208) ; The sleep interrupt will be used for timing Xtal and PLL startup.
(0209) or reg[INT_MSK0],INT_MSK0_SLEEP
(0210)
(0211) ; Wait for a SleepTimer interrupt to tell that 1 sec has passed
(0212) mov reg[INT_VC],0 ; Clear all pending interrupts
(0213) .WaitFor1s:
(0214) tst reg[INT_CLR0],INT_MSK0_SLEEP ; test the Interrupt Status
(0215) jz .WaitFor1s ; TimeOut occurs on Sleep Timer 1s
(0216)
(0217) ELSE ;!(SELECT_32K & WAIT_FOR_32K)
(0218) ; Either no ECO, or waiting for stable clock is to be done in main
(0219) M8C_SetBank1
0091: 71 10 OR F,16
(0220) mov reg[OSC_CR0],(SELECT_32K_JUST | PLL_MODE_JUST | SLEEP_TIMER_JUST | OSC_CR0_CPU_12MHz)
0093: 62 E0 0A MOV REG[224],10
(0221) M8C_SetBank0
0096: 70 EF AND F,239
(0222) M8C_ClearWDTAndSleep ; Reset the watch dog
0098: 62 E3 38 MOV REG[227],56
(0223)
(0224) ENDIF ;(SELECT_32K & WAIT_FOR_32K)
(0225)
(0226) ;-------------------------------------------------------------------------
(0227) ; Crystal is now fully operational (assuming WAIT_FOR_32K was left
(0228) ; enabled). Now start up PLL lock mode if selected.
(0229) ;-------------------------------------------------------------------------
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