psocgpioint.h

测量脉搏的源码 Cypress公司使用 CY27443 完成相关的功能

// FED address and mask defines
#pragma	ioport	FED_Data_ADDR:	0x0
BYTE			FED_Data_ADDR;
#pragma	ioport	FED_DriveMode_0_ADDR:	0x100
BYTE			FED_DriveMode_0_ADDR;
#pragma	ioport	FED_DriveMode_1_ADDR:	0x101
BYTE			FED_DriveMode_1_ADDR;
#pragma	ioport	FED_DriveMode_2_ADDR:	0x3
BYTE			FED_DriveMode_2_ADDR;
#pragma	ioport	FED_GlobalSelect_ADDR:	0x2
BYTE			FED_GlobalSelect_ADDR;
#pragma	ioport	FED_IntCtrl_0_ADDR:	0x102
BYTE			FED_IntCtrl_0_ADDR;
#pragma	ioport	FED_IntCtrl_1_ADDR:	0x103
BYTE			FED_IntCtrl_1_ADDR;
#pragma	ioport	FED_IntEn_ADDR:	0x1
BYTE			FED_IntEn_ADDR;
#define FED_MASK 0x2
// BIAS address and mask defines
#pragma	ioport	BIAS_Data_ADDR:	0x0
BYTE			BIAS_Data_ADDR;
#pragma	ioport	BIAS_DriveMode_0_ADDR:	0x100
BYTE			BIAS_DriveMode_0_ADDR;
#pragma	ioport	BIAS_DriveMode_1_ADDR:	0x101
BYTE			BIAS_DriveMode_1_ADDR;
#pragma	ioport	BIAS_DriveMode_2_ADDR:	0x3
BYTE			BIAS_DriveMode_2_ADDR;
#pragma	ioport	BIAS_GlobalSelect_ADDR:	0x2
BYTE			BIAS_GlobalSelect_ADDR;
#pragma	ioport	BIAS_IntCtrl_0_ADDR:	0x102
BYTE			BIAS_IntCtrl_0_ADDR;
#pragma	ioport	BIAS_IntCtrl_1_ADDR:	0x103
BYTE			BIAS_IntCtrl_1_ADDR;
#pragma	ioport	BIAS_IntEn_ADDR:	0x1
BYTE			BIAS_IntEn_ADDR;
#define BIAS_MASK 0x8
// AnalogOutBuf_2 address and mask defines
#pragma	ioport	AnalogOutBuf_2_Data_ADDR:	0x0
BYTE			AnalogOutBuf_2_Data_ADDR;
#pragma	ioport	AnalogOutBuf_2_DriveMode_0_ADDR:	0x100
BYTE			AnalogOutBuf_2_DriveMode_0_ADDR;
#pragma	ioport	AnalogOutBuf_2_DriveMode_1_ADDR:	0x101
BYTE			AnalogOutBuf_2_DriveMode_1_ADDR;
#pragma	ioport	AnalogOutBuf_2_DriveMode_2_ADDR:	0x3
BYTE			AnalogOutBuf_2_DriveMode_2_ADDR;
#pragma	ioport	AnalogOutBuf_2_GlobalSelect_ADDR:	0x2
BYTE			AnalogOutBuf_2_GlobalSelect_ADDR;
#pragma	ioport	AnalogOutBuf_2_IntCtrl_0_ADDR:	0x102
BYTE			AnalogOutBuf_2_IntCtrl_0_ADDR;
#pragma	ioport	AnalogOutBuf_2_IntCtrl_1_ADDR:	0x103
BYTE			AnalogOutBuf_2_IntCtrl_1_ADDR;
#pragma	ioport	AnalogOutBuf_2_IntEn_ADDR:	0x1
BYTE			AnalogOutBuf_2_IntEn_ADDR;
#define AnalogOutBuf_2_MASK 0x10
// Detector address and mask defines
#pragma	ioport	Detector_Data_ADDR:	0x0
BYTE			Detector_Data_ADDR;
#pragma	ioport	Detector_DriveMode_0_ADDR:	0x100
BYTE			Detector_DriveMode_0_ADDR;
#pragma	ioport	Detector_DriveMode_1_ADDR:	0x101
BYTE			Detector_DriveMode_1_ADDR;
#pragma	ioport	Detector_DriveMode_2_ADDR:	0x3
BYTE			Detector_DriveMode_2_ADDR;
#pragma	ioport	Detector_GlobalSelect_ADDR:	0x2
BYTE			Detector_GlobalSelect_ADDR;
#pragma	ioport	Detector_IntCtrl_0_ADDR:	0x102
BYTE			Detector_IntCtrl_0_ADDR;
#pragma	ioport	Detector_IntCtrl_1_ADDR:	0x103
BYTE			Detector_IntCtrl_1_ADDR;
#pragma	ioport	Detector_IntEn_ADDR:	0x1
BYTE			Detector_IntEn_ADDR;
#define Detector_MASK 0x20
// LCD_RST address and mask defines
#pragma	ioport	LCD_RST_Data_ADDR:	0x4
BYTE			LCD_RST_Data_ADDR;
#pragma	ioport	LCD_RST_DriveMode_0_ADDR:	0x104
BYTE			LCD_RST_DriveMode_0_ADDR;
#pragma	ioport	LCD_RST_DriveMode_1_ADDR:	0x105
BYTE			LCD_RST_DriveMode_1_ADDR;
#pragma	ioport	LCD_RST_DriveMode_2_ADDR:	0x7
BYTE			LCD_RST_DriveMode_2_ADDR;
#pragma	ioport	LCD_RST_GlobalSelect_ADDR:	0x6
BYTE			LCD_RST_GlobalSelect_ADDR;
#pragma	ioport	LCD_RST_IntCtrl_0_ADDR:	0x106
BYTE			LCD_RST_IntCtrl_0_ADDR;
#pragma	ioport	LCD_RST_IntCtrl_1_ADDR:	0x107
BYTE			LCD_RST_IntCtrl_1_ADDR;
#pragma	ioport	LCD_RST_IntEn_ADDR:	0x5
BYTE			LCD_RST_IntEn_ADDR;
#define LCD_RST_MASK 0x2
// LCD_CLK address and mask defines
#pragma	ioport	LCD_CLK_Data_ADDR:	0x4
BYTE			LCD_CLK_Data_ADDR;
#pragma	ioport	LCD_CLK_DriveMode_0_ADDR:	0x104
BYTE			LCD_CLK_DriveMode_0_ADDR;
#pragma	ioport	LCD_CLK_DriveMode_1_ADDR:	0x105
BYTE			LCD_CLK_DriveMode_1_ADDR;
#pragma	ioport	LCD_CLK_DriveMode_2_ADDR:	0x7
BYTE			LCD_CLK_DriveMode_2_ADDR;
#pragma	ioport	LCD_CLK_GlobalSelect_ADDR:	0x6
BYTE			LCD_CLK_GlobalSelect_ADDR;
#pragma	ioport	LCD_CLK_IntCtrl_0_ADDR:	0x106
BYTE			LCD_CLK_IntCtrl_0_ADDR;
#pragma	ioport	LCD_CLK_IntCtrl_1_ADDR:	0x107
BYTE			LCD_CLK_IntCtrl_1_ADDR;
#pragma	ioport	LCD_CLK_IntEn_ADDR:	0x5
BYTE			LCD_CLK_IntEn_ADDR;
#define LCD_CLK_MASK 0x4
// PULSE_LED address and mask defines
#pragma	ioport	PULSE_LED_Data_ADDR:	0x4
BYTE			PULSE_LED_Data_ADDR;
#pragma	ioport	PULSE_LED_DriveMode_0_ADDR:	0x104
BYTE			PULSE_LED_DriveMode_0_ADDR;
#pragma	ioport	PULSE_LED_DriveMode_1_ADDR:	0x105
BYTE			PULSE_LED_DriveMode_1_ADDR;
#pragma	ioport	PULSE_LED_DriveMode_2_ADDR:	0x7
BYTE			PULSE_LED_DriveMode_2_ADDR;
#pragma	ioport	PULSE_LED_GlobalSelect_ADDR:	0x6
BYTE			PULSE_LED_GlobalSelect_ADDR;
#pragma	ioport	PULSE_LED_IntCtrl_0_ADDR:	0x106
BYTE			PULSE_LED_IntCtrl_0_ADDR;
#pragma	ioport	PULSE_LED_IntCtrl_1_ADDR:	0x107
BYTE			PULSE_LED_IntCtrl_1_ADDR;
#pragma	ioport	PULSE_LED_IntEn_ADDR:	0x5
BYTE			PULSE_LED_IntEn_ADDR;
#define PULSE_LED_MASK 0x8
// LCD_DATA address and mask defines
#pragma	ioport	LCD_DATA_Data_ADDR:	0x4
BYTE			LCD_DATA_Data_ADDR;
#pragma	ioport	LCD_DATA_DriveMode_0_ADDR:	0x104
BYTE			LCD_DATA_DriveMode_0_ADDR;
#pragma	ioport	LCD_DATA_DriveMode_1_ADDR:	0x105
BYTE			LCD_DATA_DriveMode_1_ADDR;
#pragma	ioport	LCD_DATA_DriveMode_2_ADDR:	0x7
BYTE			LCD_DATA_DriveMode_2_ADDR;
#pragma	ioport	LCD_DATA_GlobalSelect_ADDR:	0x6
BYTE			LCD_DATA_GlobalSelect_ADDR;
#pragma	ioport	LCD_DATA_IntCtrl_0_ADDR:	0x106
BYTE			LCD_DATA_IntCtrl_0_ADDR;
#pragma	ioport	LCD_DATA_IntCtrl_1_ADDR:	0x107
BYTE			LCD_DATA_IntCtrl_1_ADDR;
#pragma	ioport	LCD_DATA_IntEn_ADDR:	0x5
BYTE			LCD_DATA_IntEn_ADDR;
#define LCD_DATA_MASK 0x10
// LCD_DC address and mask defines
#pragma	ioport	LCD_DC_Data_ADDR:	0x4
BYTE			LCD_DC_Data_ADDR;
#pragma	ioport	LCD_DC_DriveMode_0_ADDR:	0x104
BYTE			LCD_DC_DriveMode_0_ADDR;
#pragma	ioport	LCD_DC_DriveMode_1_ADDR:	0x105
BYTE			LCD_DC_DriveMode_1_ADDR;
#pragma	ioport	LCD_DC_DriveMode_2_ADDR:	0x7
BYTE			LCD_DC_DriveMode_2_ADDR;
#pragma	ioport	LCD_DC_GlobalSelect_ADDR:	0x6
BYTE			LCD_DC_GlobalSelect_ADDR;
#pragma	ioport	LCD_DC_IntCtrl_0_ADDR:	0x106
BYTE			LCD_DC_IntCtrl_0_ADDR;
#pragma	ioport	LCD_DC_IntCtrl_1_ADDR:	0x107
BYTE			LCD_DC_IntCtrl_1_ADDR;
#pragma	ioport	LCD_DC_IntEn_ADDR:	0x5
BYTE			LCD_DC_IntEn_ADDR;
#define LCD_DC_MASK 0x40
// MOD_LED address and mask defines
#pragma	ioport	MOD_LED_Data_ADDR:	0x8
BYTE			MOD_LED_Data_ADDR;
#pragma	ioport	MOD_LED_DriveMode_0_ADDR:	0x108
BYTE			MOD_LED_DriveMode_0_ADDR;
#pragma	ioport	MOD_LED_DriveMode_1_ADDR:	0x109
BYTE			MOD_LED_DriveMode_1_ADDR;
#pragma	ioport	MOD_LED_DriveMode_2_ADDR:	0xb
BYTE			MOD_LED_DriveMode_2_ADDR;
#pragma	ioport	MOD_LED_GlobalSelect_ADDR:	0xa
BYTE			MOD_LED_GlobalSelect_ADDR;
#pragma	ioport	MOD_LED_IntCtrl_0_ADDR:	0x10a
BYTE			MOD_LED_IntCtrl_0_ADDR;
#pragma	ioport	MOD_LED_IntCtrl_1_ADDR:	0x10b
BYTE			MOD_LED_IntCtrl_1_ADDR;
#pragma	ioport	MOD_LED_IntEn_ADDR:	0x9
BYTE			MOD_LED_IntEn_ADDR;
#define MOD_LED_MASK 0x2
// Reset_Button address and mask defines
#pragma	ioport	Reset_Button_Data_ADDR:	0x8
BYTE			Reset_Button_Data_ADDR;
#pragma	ioport	Reset_Button_DriveMode_0_ADDR:	0x108
BYTE			Reset_Button_DriveMode_0_ADDR;
#pragma	ioport	Reset_Button_DriveMode_1_ADDR:	0x109
BYTE			Reset_Button_DriveMode_1_ADDR;
#pragma	ioport	Reset_Button_DriveMode_2_ADDR:	0xb
BYTE			Reset_Button_DriveMode_2_ADDR;
#pragma	ioport	Reset_Button_GlobalSelect_ADDR:	0xa
BYTE			Reset_Button_GlobalSelect_ADDR;
#pragma	ioport	Reset_Button_IntCtrl_0_ADDR:	0x10a
BYTE			Reset_Button_IntCtrl_0_ADDR;
#pragma	ioport	Reset_Button_IntCtrl_1_ADDR:	0x10b
BYTE			Reset_Button_IntCtrl_1_ADDR;
#pragma	ioport	Reset_Button_IntEn_ADDR:	0x9
BYTE			Reset_Button_IntEn_ADDR;
#define Reset_Button_MASK 0x8
// Mode_Button address and mask defines
#pragma	ioport	Mode_Button_Data_ADDR:	0x8
BYTE			Mode_Button_Data_ADDR;
#pragma	ioport	Mode_Button_DriveMode_0_ADDR:	0x108
BYTE			Mode_Button_DriveMode_0_ADDR;
#pragma	ioport	Mode_Button_DriveMode_1_ADDR:	0x109
BYTE			Mode_Button_DriveMode_1_ADDR;
#pragma	ioport	Mode_Button_DriveMode_2_ADDR:	0xb
BYTE			Mode_Button_DriveMode_2_ADDR;
#pragma	ioport	Mode_Button_GlobalSelect_ADDR:	0xa
BYTE			Mode_Button_GlobalSelect_ADDR;
#pragma	ioport	Mode_Button_IntCtrl_0_ADDR:	0x10a
BYTE			Mode_Button_IntCtrl_0_ADDR;
#pragma	ioport	Mode_Button_IntCtrl_1_ADDR:	0x10b
BYTE			Mode_Button_IntCtrl_1_ADDR;
#pragma	ioport	Mode_Button_IntEn_ADDR:	0x9
BYTE			Mode_Button_IntEn_ADDR;
#define Mode_Button_MASK 0x20