📄 spimint.lis
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0005 OSC_CR0_CPU_750kHz: equ 05h ; set CPU Freq bits for 750kHz Operation
0006 OSC_CR0_CPU_187d5kHz: equ 06h ; set CPU Freq bits for 187.5kHz Operation
0007 OSC_CR0_CPU_93d7kHz: equ 07h ; set CPU Freq bits for 93.7kHz Operation
0000
00E1 OSC_CR1: equ E1h ; System VC1/VC2 Divider Control Register (RW)
00F0 OSC_CR1_VC1: equ F0h ; MASK: System VC1 24MHz/External Clk divider
000F OSC_CR1_VC2: equ 0Fh ; MASK: System VC2 24MHz/External Clk divider
0000
00E2 OSC_CR2: equ E2h ; Oscillator Control Register 2 (RW)
0004 OSC_CR2_EXTCLKEN: equ 04h ; MASK: Enable/Disable External Clock
0002 OSC_CR2_IMODIS: equ 02h ; MASK: Enable/Disable System (IMO) Clock Net
0001 OSC_CR2_SYSCLKX2DIS: equ 01h ; MASK: Enable/Disable 48MHz clock source
0000
00E3 VLT_CR: equ E3h ; Voltage Monitor Control Register (RW)
0080 VLT_CR_SMP: equ 80h ; MASK: Enable Switch Mode Pump
0030 VLT_CR_PORLEV: equ 30h ; MASK: Mask for Power on Reset level control
0000 VLT_CR_3V0_POR: equ 00h ; MASK: Set the Precision POR to 3.0V
0010 VLT_CR_4V5_POR: equ 10h ; MASK: Set the Precision POR to 4.5V
0020 VLT_CR_4V75_POR: equ 20h ; MASK: Set the Precision POR to 4.75V
0030 VLT_CR_DISABLE: equ 30h ; MASK: Disable the Precision POR
0008 VLT_CR_LVDTBEN: equ 08h ; MASK: Enable the CPU Throttle Back on LVD
0007 VLT_CR_VM: equ 07h ; MASK: Mask for Voltage Monitor level setting
0000
00E4 VLT_CMP: equ E4h ; Voltage Monitor Comparators Register (R)
0008 VLT_CMP_PUMP: equ 08h ; MASK: Vcc below SMP trip level
0008 VLT_CMP_LVD: equ 08h ; MASK: Vcc below LVD trip level
0008 VLT_CMP_PPOR: equ 08h ; MASK: Vcc below PPOR trip level
0000
00E8 IMO_TR: equ E8h ; Internal Main Oscillator Trim Register (W)
00E9 ILO_TR: equ E9h ; Internal Low-speed Oscillator Trim (W)
00EA BDG_TR: equ EAh ; Band Gap Trim Register (W)
00EB ECO_TR: equ EBh ; External Oscillator Trim Register (W)
0000
0000 ;;=============================================================================
0000 ;; M8C System Macros
0000 ;; These macros should be used when their functions are needed.
0000 ;;=============================================================================
0000
0000 ;----------------------------------------------------
0000 ; Swapping Register Banks
0000 ;----------------------------------------------------
0000 macro M8C_SetBank0
0000 and F, ~FLAG_XIO_MASK
0000 macro M8C_SetBank1
0000 or F, FLAG_XIO_MASK
0000 macro M8C_EnableGInt
0000 or F, FLAG_GLOBAL_IE
0000 macro M8C_DisableGInt
0000 and F, ~FLAG_GLOBAL_IE
0000 macro M8C_DisableIntMask
0000 and reg[@0], ~@1 ; disable specified interrupt enable bit
0000 macro M8C_EnableIntMask
0000 or reg[@0], @1 ; enable specified interrupt enable bit
0000 macro M8C_ClearIntFlag
0000 and reg[@0], ~@1 ; clear specified interrupt enable bit
0000 macro M8C_EnableWatchDog
0000 and reg[CPU_SCR0], ~CPU_SCR0_PORS_MASK
0000 macro M8C_ClearWDT
0000 mov reg[RES_WDT], 00h
0000 macro M8C_ClearWDTAndSleep
0000 mov reg[RES_WDT], 38h
0000 macro M8C_Stall
0000 or reg[ASY_CR], ASY_CR_SYNCEN
0000 macro M8C_Unstall
0000 and reg[ASY_CR], ~ASY_CR_SYNCEN
0000 macro M8C_Sleep
0000 or reg[CPU_SCR0], CPU_SCR0_SLEEP_MASK
0000 ; The next instruction to be executed depends on the state of the
0000 ; various interrupt enable bits. If some interrupts are enabled
0000 ; and the global interrupts are disabled, the next instruction will
0000 ; be the one that follows the invocation of this macro. If global
0000 ; interrupts are also enabled then the next instruction will be
0000 ; from the interrupt vector table. If no interrupts are enabled
0000 ; then the CPU sleeps forever.
0000 macro M8C_Stop
0000 ; In general, you probably don't want to do this, but here's how:
0000 or reg[CPU_SCR0], CPU_SCR0_STOP_MASK
0000 ; Next instruction to be executed is located in the interrupt
0000 ; vector table entry for Power-On Reset.
0000 macro M8C_Reset
0000 ; Restore CPU to the power-on reset state.
0000 mov A, 0
0000 SSC
0000 ; Next non-supervisor instruction will be at interrupt vector 0.
0000 macro Suspend_CodeCompressor
0000 or F, 0
0000 macro Resume_CodeCompressor
0000 add SP, 0
0080 SPIM_bINT_MASK: equ 80h
0000 ; SPIM interrupt address
00E1 SPIM_INT_REG: equ 0e1h
0000
0000 ; Do not use, this equate will be removed in a future release
0080 bSPIM_INT_MASK: equ 80h
0000
0000 ;--------------------------------------------------
0000 ; Register constants and masks
0000 ;--------------------------------------------------
0000 SPIM_SPIM_MODE_0: equ 00h ;MODE 0 - Leading edge latches data - pos clock
0002 SPIM_SPIM_MODE_1: equ 02h ;MODE 1 - Leading edge latches data - neg clock
0004 SPIM_SPIM_MODE_2: equ 04h ;MODE 2 - Trailing edge latches data - pos clock
0006 SPIM_SPIM_MODE_3: equ 06h ;MODE 3 - Trailing edge latches data - neg clock
0080 SPIM_SPIM_LSB_FIRST: equ 80h ;LSB bit transmitted/received first
0000 SPIM_SPIM_MSB_FIRST: equ 00h ;MSB bit transmitted/received first
0000
0000 ;---------------------------
0000 ; SPI Status register masks
0000 ;---------------------------
0040 SPIM_SPIM_RX_OVERRUN_ERROR: equ 40h ;Overrun error in received data
0010 SPIM_SPIM_TX_BUFFER_EMPTY: equ 10h ;TX Buffer register is ready for next data byte
0008 SPIM_SPIM_RX_BUFFER_FULL: equ 08h ;RX Buffer register has received current data
0020 SPIM_SPIM_SPI_COMPLETE: equ 20h ;SPI Tx/Rx cycle has completed
0000
0000 ;--------------------------------------------------
0000 ; Registers used by SPIM
0000 ;--------------------------------------------------
003F SPIM_CONTROL_REG: equ 3fh ;Control register
003C SPIM_SHIFT_REG: equ 3ch ;TX Shift Register register
003D SPIM_TX_BUFFER_REG: equ 3dh ;TX Buffer Register
003E SPIM_RX_BUFFER_REG: equ 3eh ;RX Buffer Register
003C SPIM_FUNCTION_REG: equ 3ch ;Function register
003D SPIM_INPUT_REG: equ 3dh ;Input register
003E SPIM_OUTPUT_REG: equ 3eh ;Output register
0000
0000 ; end of file SPIM.inc
0000
0000
0000 ;-----------------------------------------------
0000 ; Global Symbols
0000 ;-----------------------------------------------
export _SPIM_ISR
AREA bss (RAM,REL)
;@PSoC_UserCode_INIT@ (Do not change this line.)
;---------------------------------------------------
; Insert your custom declarations below this banner
;---------------------------------------------------
;---------------------------------------------------
; Insert your custom declarations above this banner
;---------------------------------------------------
;@PSoC_UserCode_END@ (Do not change this line.)
AREA UserModules (ROM, REL)
;-----------------------------------------------------------------------------
; FUNCTION NAME: _SPIM_ISR
;
; DESCRIPTION: Unless modified, this implements only a null handler stub.
;
;-----------------------------------------------------------------------------
;
0000 _SPIM_ISR:
0000
0000 ;@PSoC_UserCode_BODY@ (Do not change this line.)
0000 ;---------------------------------------------------
0000 ; Insert your custom code below this banner
0000 ;---------------------------------------------------
0000
0000 ;---------------------------------------------------
0000 ; Insert your custom code above this banner
0000 ;---------------------------------------------------
0000 ;@PSoC_UserCode_END@ (Do not change this line.)
0000
0000 7E reti
0001
0001
0001 ; end of file SPIMINT.asm
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