📄 route.lis
字号:
0000 ;;*****************************************************************************
0000 ;;*****************************************************************************
0000 ;; FILENAME: Route.asm
0000 ;; Version: 2.1, Updated on 2003/08/26 at 16:07:58
0000 ;; Generated by PSoC Designer ver 4.0 b865 : 27 August, 2003
0000 ;;
0000 ;; DESCRIPTION: SCBLOCK User Module software implementation file for the
0000 ;; 22/24/25/26/27xxx PSoC family of devices.
0000 ;;
0000 ;;-----------------------------------------------------------------------------
0000 ;; Copyright (c) Cypress MicroSystems 2000-2003. All Rights Reserved.
0000 ;;*****************************************************************************
0000 ;;*****************************************************************************
0000
0000
0000 ;; -----------------------------------------------------------------
0000 ;; Register Definitions
0000 ;; -----------------------------------------------------------------
0000 ;; BIT FIELD Mask
0000 ;; ----------------- -----
0000 ;; CR0.FCap 80
0000 ;; CR0.ClockPhase 40
0000 ;; CR0.ASign 20
0000 ;; CR0.ACap 1F
0000 ;;
0000 ;; CR1.AMux C0 SCB
0000 ;; CR1.ACMux C0 SCA
0000 ;; CR1.BCap 1F
0000 ;;
0000 ;; CR2.AnalogBus 80
0000 ;; CR2.CmpBus 40
0000 ;; CR2.AutoZero 20
0000 ;; CR2.CCap 1F
0000 ;;
0000 ;; CR3.RefSelect C0
0000 ;; CR3.FSW1 20
0000 ;; CR3.FSW0 10
0000 ;; CR3.BSW 08 SCB
0000 ;; CR3.BMux 04 SCB
0000 ;; CR3.BMux 0C SCA
0000 ;; CR3.Power 03
0000 ;;
0000
0000 Route_OFF: equ 0
0001 Route_LOWPOWER: equ 1
0002 Route_MEDPOWER: equ 2
0003 Route_HIGHPOWER: equ 3
0000
0000 ;--------------------------------------------------
0000 ; Register Address Constants for Route
0000 ;--------------------------------------------------
0084 Route_cr0: equ 84h
0085 Route_cr1: equ 85h
0086 Route_cr2: equ 86h
0087 Route_cr3: equ 87h
0000 Route_Comp_Ctrl: equ 0h
0000
0000 ; end of file Route.inc
0000
0000
0000
0000
0000
0010 FLAG_XIO_MASK: equ 10h
0008 FLAG_SUPER: equ 08h
0004 FLAG_CARRY: equ 04h
0002 FLAG_ZERO: equ 02h
0001 FLAG_GLOBAL_IE: equ 01h
0000
0000
0000 ;;=============================================================================
0000 ;; Register Space, Bank 0
0000 ;;=============================================================================
0000
0000 ;------------------------------------------------
0000 ; Port Registers
0000 ; Note: Also see this address range in Bank 1.
0000 ;------------------------------------------------
0000 ; Port 0
0000 PRT0DR: equ 00h ; Port 0 Data Register (RW)
0001 PRT0IE: equ 01h ; Port 0 Interrupt Enable Register (RW)
0002 PRT0GS: equ 02h ; Port 0 Global Select Register (RW)
0003 PRT0DM2: equ 03h ; Port 0 Drive Mode 2 (RW)
0000 ; Port 1
0004 PRT1DR: equ 04h ; Port 1 Data Register (RW)
0005 PRT1IE: equ 05h ; Port 1 Interrupt Enable Register (RW)
0006 PRT1GS: equ 06h ; Port 1 Global Select Register (RW)
0007 PRT1DM2: equ 07h ; Port 1 Drive Mode 2 (RW)
0000 ; Port 2
0008 PRT2DR: equ 08h ; Port 2 Data Register (RW)
0009 PRT2IE: equ 09h ; Port 2 Interrupt Enable Register (RW)
000A PRT2GS: equ 0Ah ; Port 2 Global Select Register (RW)
000B PRT2DM2: equ 0Bh ; Port 2 Drive Mode 2 (RW)
0000 ; Port 3
000C PRT3DR: equ 0Ch ; Port 3 Data Register (RW)
000D PRT3IE: equ 0Dh ; Port 3 Interrupt Enable Register (RW)
000E PRT3GS: equ 0Eh ; Port 3 Global Select Register (RW)
000F PRT3DM2: equ 0Fh ; Port 3 Drive Mode 2 (RW)
0000 ; Port 4
0010 PRT4DR: equ 10h ; Port 4 Data Register (RW)
0011 PRT4IE: equ 11h ; Port 4 Interrupt Enable Register (RW)
0012 PRT4GS: equ 12h ; Port 4 Global Select Register (RW)
0013 PRT4DM2: equ 13h ; Port 4 Drive Mode 2 (RW)
0000 ; Port 5
0014 PRT5DR: equ 14h ; Port 5 Data Register (RW)
0015 PRT5IE: equ 15h ; Port 5 Interrupt Enable Register (RW)
0016 PRT5GS: equ 16h ; Port 5 Global Select Register (RW)
0017 PRT5DM2: equ 17h ; Port 5 Drive Mode 2 (RW)
0000
0000 ;------------------------------------------------
0000 ; Digital PSoC(tm) block Registers
0000 ; Note: Also see this address range in Bank 1.
0000 ;------------------------------------------------
0000 ; # Access is bit specific. Refer to indicated page for details
0000 ; Digital PSoC block 00, Basic Type B
0020 DBB00DR0: equ 20h ; data register 0 (#)
0021 DBB00DR1: equ 21h ; data register 1 (W)
0022 DBB00DR2: equ 22h ; data register 2 (RW)
0023 DBB00CR0: equ 23h ; control & status register 0 (#)
0000
0000 ; Digital PSoC block 01, Basic Type B
0024 DBB01DR0: equ 24h ; data register 0 (#)
0025 DBB01DR1: equ 25h ; data register 1 (W)
0026 DBB01DR2: equ 26h ; data register 2 (RW)
0027 DBB01CR0: equ 27h ; control & status register 0 (#)
0000
0000 ; Digital PSoC block 02, Communications Type B
0028 DCB02DR0: equ 28h ; data register 0 (#)
0029 DCB02DR1: equ 29h ; data register 1 (W)
002A DCB02DR2: equ 2Ah ; data register 2 (RW)
002B DCB02CR0: equ 2Bh ; control & status register 0 (#)
0000
0000 ; Digital PSoC block 03, Communications Type B
002C DCB03DR0: equ 2Ch ; data register 0 (#)
002D DCB03DR1: equ 2Dh ; data register 1 (W)
002E DCB03DR2: equ 2Eh ; data register 2 (RW)
002F DCB03CR0: equ 2Fh ; control & status register 0 (#)
0000
0000 ; Digital PSoC block 10, Basic Type B
0030 DBB10DR0: equ 30h ; data register 0 (#)
0031 DBB10DR1: equ 31h ; data register 1 (W)
0032 DBB10DR2: equ 32h ; data register 2 (RW)
0033 DBB10CR0: equ 33h ; control & status register 0 (#)
0000
0000 ; Digital PSoC block 11, Basic Type B
0034 DBB11DR0: equ 34h ; data register 0 (#)
0035 DBB11DR1: equ 35h ; data register 1 (W)
0036 DBB11DR2: equ 36h ; data register 2 (RW)
0037 DBB11CR0: equ 37h ; control & status register 0 (#)
0000
0000 ; Digital PSoC block 12, Communications Type B
0038 DCB12DR0: equ 38h ; data register 0 (#)
0039 DCB12DR1: equ 39h ; data register 1 (W)
003A DCB12DR2: equ 3Ah ; data register 2 (RW)
003B DCB12CR0: equ 3Bh ; control & status register 0 (#)
0000
0000 ; Digital PSoC block 13, Communications Type B
003C DCB13DR0: equ 3Ch ; data register 0 (#)
003D DCB13DR1: equ 3Dh ; data register 1 (W)
003E DCB13DR2: equ 3Eh ; data register 2 (RW)
003F DCB13CR0: equ 3Fh ; control & status register 0 (#)
0000
0000 ;-------------------------------------
0000 ; Analog Resource Control Registers
0000 ;-------------------------------------
0060 AMX_IN: equ 60h ; Analog Input Multiplexor Control (RW)
00C0 AMX_IN_ACI3: equ C0h ; MASK: column 3 input mux
0030 AMX_IN_ACI2: equ 30h ; MASK: column 2 input mux
000C AMX_IN_ACI1: equ 0Ch ; MASK: column 1 input mux
0003 AMX_IN_ACI0: equ 03h ; MASK: column 0 input mux
0000
0063 ARF_CR: equ 63h ; Analog Reference Control Register (RW)
0040 ARF_CR_HBE: equ 40h ; MASK: Bias level control
0038 ARF_CR_REF: equ 38h ; MASK: Analog array ref control
0004 ARF_CR_APWR: equ 04h ; MASK: Analog Power
0003 ARF_CR_SCPWR: equ 03h ; MASK: Switched Cap block power
0000
0064 CMP_CR0: equ 64h ; Analog Comparator Bus 0 Register (#)
0080 CMP_CR0_COMP3: equ 80h ; MASK: Column 3 comparator state (R)
0040 CMP_CR0_COMP2: equ 40h ; MASK: Column 2 comparator state (R)
0020 CMP_CR0_COMP1: equ 20h ; MASK: Column 1 comparator state (R)
0010 CMP_CR0_COMP0: equ 10h ; MASK: Column 0 comparator state (R)
0008 CMP_CR0_AINT3: equ 08h ; MASK: Column 3 interrupt source (RW)
0004 CMP_CR0_AINT2: equ 04h ; MASK: Column 2 interrupt source (RW)
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -