📄 in_pga.lis
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0030 VLT_CR_PORLEV: equ 30h ; MASK: Mask for Power on Reset level control
0000 VLT_CR_3V0_POR: equ 00h ; MASK: Set the Precision POR to 3.0V
0010 VLT_CR_4V5_POR: equ 10h ; MASK: Set the Precision POR to 4.5V
0020 VLT_CR_4V75_POR: equ 20h ; MASK: Set the Precision POR to 4.75V
0030 VLT_CR_DISABLE: equ 30h ; MASK: Disable the Precision POR
0008 VLT_CR_LVDTBEN: equ 08h ; MASK: Enable the CPU Throttle Back on LVD
0007 VLT_CR_VM: equ 07h ; MASK: Mask for Voltage Monitor level setting
0000
00E4 VLT_CMP: equ E4h ; Voltage Monitor Comparators Register (R)
0008 VLT_CMP_PUMP: equ 08h ; MASK: Vcc below SMP trip level
0008 VLT_CMP_LVD: equ 08h ; MASK: Vcc below LVD trip level
0008 VLT_CMP_PPOR: equ 08h ; MASK: Vcc below PPOR trip level
0000
00E8 IMO_TR: equ E8h ; Internal Main Oscillator Trim Register (W)
00E9 ILO_TR: equ E9h ; Internal Low-speed Oscillator Trim (W)
00EA BDG_TR: equ EAh ; Band Gap Trim Register (W)
00EB ECO_TR: equ EBh ; External Oscillator Trim Register (W)
0000
0000 ;;=============================================================================
0000 ;; M8C System Macros
0000 ;; These macros should be used when their functions are needed.
0000 ;;=============================================================================
0000
0000 ;----------------------------------------------------
0000 ; Swapping Register Banks
0000 ;----------------------------------------------------
0000 macro M8C_SetBank0
0000 and F, ~FLAG_XIO_MASK
0000 macro M8C_SetBank1
0000 or F, FLAG_XIO_MASK
0000 macro M8C_EnableGInt
0000 or F, FLAG_GLOBAL_IE
0000 macro M8C_DisableGInt
0000 and F, ~FLAG_GLOBAL_IE
0000 macro M8C_DisableIntMask
0000 and reg[@0], ~@1 ; disable specified interrupt enable bit
0000 macro M8C_EnableIntMask
0000 or reg[@0], @1 ; enable specified interrupt enable bit
0000 macro M8C_ClearIntFlag
0000 and reg[@0], ~@1 ; clear specified interrupt enable bit
0000 macro M8C_EnableWatchDog
0000 and reg[CPU_SCR0], ~CPU_SCR0_PORS_MASK
0000 macro M8C_ClearWDT
0000 mov reg[RES_WDT], 00h
0000 macro M8C_ClearWDTAndSleep
0000 mov reg[RES_WDT], 38h
0000 macro M8C_Stall
0000 or reg[ASY_CR], ASY_CR_SYNCEN
0000 macro M8C_Unstall
0000 and reg[ASY_CR], ~ASY_CR_SYNCEN
0000 macro M8C_Sleep
0000 or reg[CPU_SCR0], CPU_SCR0_SLEEP_MASK
0000 ; The next instruction to be executed depends on the state of the
0000 ; various interrupt enable bits. If some interrupts are enabled
0000 ; and the global interrupts are disabled, the next instruction will
0000 ; be the one that follows the invocation of this macro. If global
0000 ; interrupts are also enabled then the next instruction will be
0000 ; from the interrupt vector table. If no interrupts are enabled
0000 ; then the CPU sleeps forever.
0000 macro M8C_Stop
0000 ; In general, you probably don't want to do this, but here's how:
0000 or reg[CPU_SCR0], CPU_SCR0_STOP_MASK
0000 ; Next instruction to be executed is located in the interrupt
0000 ; vector table entry for Power-On Reset.
0000 macro M8C_Reset
0000 ; Restore CPU to the power-on reset state.
0000 mov A, 0
0000 SSC
0000 ; Next non-supervisor instruction will be at interrupt vector 0.
0000 macro Suspend_CodeCompressor
0000 or F, 0
0000 macro Resume_CodeCompressor
0000 add SP, 0
export In_PGA_Start
export _In_PGA_Start
export In_PGA_SetPower
export _In_PGA_SetPower
export In_PGA_SetGain
export _In_PGA_SetGain
export In_PGA_Stop
export _In_PGA_Stop
;-----------------------------------------------
; EQUATES
;-----------------------------------------------
0003 POWERMASK: equ 03h
00F8 GAINREGMASK: equ f8h
00FC GAINMASK: equ fCh
0004 HIGHGAIN: equ 04h
0018 HIGHGAINMASK: equ 18h
0001 EXGAIN: equ 01h
0000
AREA UserModules (ROM, REL)
0000 .SECTION
0000 ;-----------------------------------------------------------------------------
0000 ; FUNCTION NAME: In_PGA_Start
0000 ; FUNCTION NAME: In_PGA_SetPower
0000 ;
0000 ; DESCRIPTION:
0000 ; Applies power setting to the module's PSoC block.
0000 ;-----------------------------------------------------------------------------
0000 ;
0000 ; ARGUMENTS:
0000 ; A Contains the power settings 0=Off, 1=Low, 2=Med, and 3=High
0000 ;
0000 ; RETURNS: NA
0000 ;
0000 ; SIDE EFFECTS:
0000 ; RESISTERS ARE VOLATILE: THE A AND X REGISTERS MAY BE MODIFIED!
0000 ;
0000 ; THEORY of OPERATION or PROCEDURE:
0000 ;
0000 ;-----------------------------------------------------------------------------
0000 In_PGA_Start:
0000 _In_PGA_Start:
0000 In_PGA_SetPower:
0000 _In_PGA_SetPower:
0000
0000 2103 and A, POWERMASK ; mask A to protect unchanged bits
0002 4F mov X, SP ; define temp store location
0003 ;
0003 08 push A ; put power value in temp store
0004 5D73 mov A, reg[In_PGA_GAIN_CR2] ; read power value
0006 21FC and A, ~POWERMASK ; clear power bits in A
0008 2B00 or A, [X] ; combine power value with balance of reg.
000A 6073 mov reg[In_PGA_GAIN_CR2], A ; move complete value back to register
000C 18 pop A
000D 7F ret
000E .ENDSECTION
000E
000E .SECTION
000E ;-----------------------------------------------------------------------------
000E ; FUNCTION NAME: In_PGA_SetGain
000E ;
000E ; DESCRIPTION:
000E ; This function sets the Gain/Atten of the amplifier. Valid gain settings
000E ; are defined in the .inc file.
000E ;
000E ;-----------------------------------------------------------------------------
000E ;
000E ; ARGUMENTS:
000E ; A Contains gain settings.
000E ;
000E ; Gain values shown are for example. (See .inc file for gain equates)
000E ;
000E ; RETURNS: NA
000E ;
000E ; SIDE EFFECTS:
000E ; RESISTERS ARE VOLATILE: THE A AND X REGISTERS MAY BE MODIFIED!
000E ;
000E ; THEORY of OPERATION or PROCEDURE:
000E ;
000E ;-----------------------------------------------------------------------------
000E In_PGA_SetGain:
000E _In_PGA_SetGain:
000E
000E 21FC and A, GAINMASK ; mask A to protect unchanged bits
0010 4F mov X, SP ; define temp store location
0011 ;
0011 08 push A ; put gain value in temp store
0012 5D71 mov A, reg[In_PGA_GAIN_CR0] ; read mux settings
0014 2107 and A, ~GAINREGMASK ; clear gain bits in A
0016 480004 tst [X],HIGHGAIN ; See if High Gain is set
0019 B00A jnz .SETHIGHGAIN
001B 4170FE and reg[In_PGA_GAIN_CR3],~EXGAIN ; Clear High Gain bit.
001E 2B00 or A, [X] ; combine gain value with balance of reg.
0020 6071 mov reg[In_PGA_GAIN_CR0], A ; move complete value back to register
0022 18 pop A
0023 7F ret
0024
0024 .SETHIGHGAIN:
0024 270018 and [X],HIGHGAINMASK ; Make sure we have a valid high gain
0027 2B00 or A, [X] ; combine gain value with balance of reg.
0029 6071 mov reg[In_PGA_GAIN_CR0], A ; move complete value back to register
002B 437001 or reg[In_PGA_GAIN_CR3], EXGAIN ; Set High Gain bit.
002E 18 pop A
002F 7F ret
0030 .ENDSECTION
0030
0030 .SECTION
0030 ;-----------------------------------------------------------------------------
0030 ; FUNCTION NAME: In_PGA_Stop
0030 ;
0030 ; DESCRIPTION:
0030 ; Turns off the power to the amplifier.
0030 ;
0030 ;-----------------------------------------------------------------------------
0030 ;
0030 ; ARGUMENTS: None
0030 ;
0030 ; RETURNS: NA
0030 ;
0030 ; SIDE EFFECTS:
0030 ; RESISTERS ARE VOLATILE: THE A AND X REGISTERS MAY BE MODIFIED!
0030 ;
0030 ; THEORY of OPERATION or PROCEDURE:
0030 ;
0030 ;-----------------------------------------------------------------------------
0030 In_PGA_Stop:
0030 _In_PGA_Stop:
0030
0030 4173FC and REG[In_PGA_GAIN_CR2], ~POWERMASK
0033 7F ret
0034 .ENDSECTION
0034 ; End of File In_PGA.asm
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