📄 adcint.lis
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0000
00E4 VLT_CMP: equ E4h ; Voltage Monitor Comparators Register (R)
0008 VLT_CMP_PUMP: equ 08h ; MASK: Vcc below SMP trip level
0008 VLT_CMP_LVD: equ 08h ; MASK: Vcc below LVD trip level
0008 VLT_CMP_PPOR: equ 08h ; MASK: Vcc below PPOR trip level
0000
00E8 IMO_TR: equ E8h ; Internal Main Oscillator Trim Register (W)
00E9 ILO_TR: equ E9h ; Internal Low-speed Oscillator Trim (W)
00EA BDG_TR: equ EAh ; Band Gap Trim Register (W)
00EB ECO_TR: equ EBh ; External Oscillator Trim Register (W)
0000
0000 ;;=============================================================================
0000 ;; M8C System Macros
0000 ;; These macros should be used when their functions are needed.
0000 ;;=============================================================================
0000
0000 ;----------------------------------------------------
0000 ; Swapping Register Banks
0000 ;----------------------------------------------------
0000 macro M8C_SetBank0
0000 and F, ~FLAG_XIO_MASK
0000 macro M8C_SetBank1
0000 or F, FLAG_XIO_MASK
0000 macro M8C_EnableGInt
0000 or F, FLAG_GLOBAL_IE
0000 macro M8C_DisableGInt
0000 and F, ~FLAG_GLOBAL_IE
0000 macro M8C_DisableIntMask
0000 and reg[@0], ~@1 ; disable specified interrupt enable bit
0000 macro M8C_EnableIntMask
0000 or reg[@0], @1 ; enable specified interrupt enable bit
0000 macro M8C_ClearIntFlag
0000 and reg[@0], ~@1 ; clear specified interrupt enable bit
0000 macro M8C_EnableWatchDog
0000 and reg[CPU_SCR0], ~CPU_SCR0_PORS_MASK
0000 macro M8C_ClearWDT
0000 mov reg[RES_WDT], 00h
0000 macro M8C_ClearWDTAndSleep
0000 mov reg[RES_WDT], 38h
0000 macro M8C_Stall
0000 or reg[ASY_CR], ASY_CR_SYNCEN
0000 macro M8C_Unstall
0000 and reg[ASY_CR], ~ASY_CR_SYNCEN
0000 macro M8C_Sleep
0000 or reg[CPU_SCR0], CPU_SCR0_SLEEP_MASK
0000 ; The next instruction to be executed depends on the state of the
0000 ; various interrupt enable bits. If some interrupts are enabled
0000 ; and the global interrupts are disabled, the next instruction will
0000 ; be the one that follows the invocation of this macro. If global
0000 ; interrupts are also enabled then the next instruction will be
0000 ; from the interrupt vector table. If no interrupts are enabled
0000 ; then the CPU sleeps forever.
0000 macro M8C_Stop
0000 ; In general, you probably don't want to do this, but here's how:
0000 or reg[CPU_SCR0], CPU_SCR0_STOP_MASK
0000 ; Next instruction to be executed is located in the interrupt
0000 ; vector table entry for Power-On Reset.
0000 macro M8C_Reset
0000 ; Restore CPU to the power-on reset state.
0000 mov A, 0
0000 SSC
0000 ; Next non-supervisor instruction will be at interrupt vector 0.
0000 macro Suspend_CodeCompressor
0000 or F, 0
0000 macro Resume_CodeCompressor
0000 add SP, 0
0008 ADC_bfCounter_Mask: equ 08h
00E1 ADC_bfCounter_INT_REG: equ 0e1h
0000
0000 ; PWM Constants
0004 ADC_bfPWM16_Mask: equ 04h
00E1 ADC_bfPWM16_INT_REG: equ 0e1h
0000
0000 ; Power Settings
0003 ADC_bfPOWERMASK: equ 03h
0000 ADC_OFF: equ 00h
0001 ADC_LOWPOWER: equ 01h
0002 ADC_MEDPOWER: equ 02h
0003 ADC_HIGHPOWER: equ 03h
0000
0000 ; Parameter Settings
000D ADC_bNUMBITS: equ dh
00C8 ADC_bCALCTIME: equ c8h
000D ADC_bMAXRES: equ 0Dh ; Max resolution 13 bits
0007 ADC_bMINRES: equ 07h ; Min resolution 7 bits
0008 ADC_fCOMPARE_TRUE: equ 08h ; Bit to enable compare True interrupts
0000
0000 ; Functionality constants
0010 ADC_fFSW0: equ 10h ; Switch Cap FSW0 switch enable
0001 ADC_NoAZ: equ 01h ; Set if AutoZero is not enabled
0020 ADC_fAutoZero: equ 20h ; Switch Cap AutoZero switch enable
0001 ADC_fDBLK_ENABLE: equ 01h ; Digital block enable bit
0004 ADC_fPULSE_WIDE: equ 04h ; Enable wide terminal count pulse.
0000
0000 ; fStatus definitions
0010 ADC_fDATA_READY: equ 10h ; This bit is set when data is available
000F ADC_bRES_MASK: equ 0Fh ; This bit while in integrate cycle
0000
0000 ; Data Format
0000 ADC_DATA_FORMAT: equ 0
0000
0000
0000 ;--------------------------------------------------
0000 ; Registers used by ADC
0000 ;--------------------------------------------------
0000 ; ADCINCVR PSoC Block register Definitions
0000 ; Integrator Block Register Definitions
0084 ADC_bfAtoDcr0: equ 84h
0085 ADC_bfAtoDcr1: equ 85h
0086 ADC_bfAtoDcr2: equ 86h
0087 ADC_bfAtoDcr3: equ 87h
0000
0000 ; Counter Block Register Definitions
002C ADC_fCounterFN: equ 2ch
002D ADC_fCounterSL: equ 2dh
002E ADC_fCounterOS: equ 2eh
002C ADC_bCount: equ 2ch
002D ADC_bPeriod: equ 2dh
002E ADC_bCompare: equ 2eh
002F ADC_bCounter_CR0: equ 2fh
0000
0000 ; PWM16 Block Register Definitions
0024 ADC_bfPWM_LSB_FN: equ 24h
0028 ADC_bfPWM_MSB_FN: equ 28h
0027 ADC_fPWM_LSB_CR0: equ 27h
002B ADC_fPWM_MSB_CR0: equ 2bh
0028 ADC_bPWM_Count_MSB: equ 28h
0024 ADC_bPWM_Count_LSB: equ 24h
0029 ADC_bPWM_Period_MSB: equ 29h
0025 ADC_bPWM_Period_LSB: equ 25h
002A ADC_bPWM_IntTime_MSB: equ 2ah
0026 ADC_bPWM_IntTime_LSB: equ 26h
0024 ADC_bfPWM_LSB_FN: equ 24h
0028 ADC_bfPWM_MSB_FN: equ 28h
0000
0000
0000 ; End of File ADC.inc
0000
0000
0000
0000 ;-----------------------------------------------
0000 ; Global Symbols
0000 ;-----------------------------------------------
export _ADC_CNT_ISR
export _ADC_PWM16_ISR
export ADC_cCounterU
export _ADC_iResult
export ADC_iResult
export _ADC_bfStatus
export ADC_bfStatus
export ADC_bSampC
;-----------------------------------------------
; Variable Allocation
;-----------------------------------------------
AREA bss(RAM)
0000 ADC_cCounterU: BLK 1 ;The Upper byte of the Counter
0001 _ADC_iResult:
0001 ADC_iResult: BLK 2 ;A/D value
0003 _ADC_bfStatus:
0003 ADC_bfStatus: BLK 1 ;Data Valid Flag
0004 ADC_bSampC: BLK 1 ;# of times to run A/D
0005
0005
0005 ;-----------------------------------------------
0005 ; EQUATES and TABLES
0005 ;-----------------------------------------------
0001 LowByte: equ 1
0000 HighByte: equ 0
0005
0005
0005 ;@PSoC_UserCode_INIT@ (Do not change this line.)
0005 ;---------------------------------------------------
0005 ; Insert your custom declarations below this banner
0005 ;---------------------------------------------------
0005
0005 ;---------------------------------------------------
0005 ; Insert your custom declarations above this banner
0005 ;---------------------------------------------------
0005 ;@PSoC_UserCode_END@ (Do not change this line.)
0005
AREA UserModules (ROM, REL)
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