📄 psocconfig.lis
字号:
0000 PLL_MODE_JUST: equ 0h ;PLL mode value justified
0001 SLEEP_TIMER: equ 1h ;Sleep Timer value
0018 SLEEP_TIMER_MASK: equ 18h ;Sleep Timer mask
0008 SLEEP_TIMER_JUST: equ 8h ;Sleep Timer value justified
0001 SWITCH_MODE_PUMP: equ 1h ;Switch Mode Pump setting (off)
0080 SWITCH_MODE_PUMP_MASK: equ 80h ;Switch Mode Pump mask
0080 SWITCH_MODE_PUMP_JUST: equ 80h ;Switch Mode Pump justified
0000 TRIP_VOLTAGE: equ 0h ;Trip Voltage
0000 SUPPLY_VOLTAGE: equ 0h ;Supply Voltage 1 = 5.0V
0000 ;0 = 3.3V
0001 COMM_RX_PRESENT: equ 1 ;1 = TRUE
0000 WATCHDOG_ENABLE: equ 0 ;Watchdog Enable 1 = Enable
0000
0002 CLOCK_DIV_VC1: equ 2h ;VC1 clock divider
00F0 CLOCK_DIV_VC1_MASK: equ f0h ;VC1 clock divider mask
0020 CLOCK_DIV_VC1_JUST: equ 20h ;VC1 clock divider justified
0003 CLOCK_DIV_VC2: equ 3h ;VC2 clock divider
000F CLOCK_DIV_VC2_MASK: equ fh ;VC2 clock divider mask
0003 CLOCK_DIV_VC2_JUST: equ 3h ;VC2 clock divider justified
0000 CLOCK_INPUT_VC3: equ 0h ;VC3 clock source
0003 CLOCK_INPUT_VC3_MASK: equ 3h ;VC3 clock source mask
0000 CLOCK_INPUT_VC3_JUST: equ 0h ;VC3 clock source justified
003B CLOCK_DIV_VC3: equ 3bh ;VC3 clock divider
00FF CLOCK_DIV_VC3_MASK: equ ffh ;VC3 clock divider mask
003B CLOCK_DIV_VC3_JUST: equ 3bh ;VC3 clock divider justified
0001 ANALOG_BUFFER_PWR: equ 1h ;Analog buffer power level
0001 ANALOG_BUFFER_PWR_MASK: equ 1h ;Analog buffer power level mask
0001 ANALOG_BUFFER_PWR_JUST: equ 1h ;Analog buffer power level justified
0007 ANALOG_POWER: equ 7h ;Analog power control
0007 ANALOG_POWER_MASK: equ 7h ;Analog power control mask
0007 ANALOG_POWER_JUST: equ 7h ;Analog power control justified
0001 OP_AMP_BIAS: equ 1h ;Op amp bias level
0040 OP_AMP_BIAS_MASK: equ 40h ;Op amp bias level mask
0040 OP_AMP_BIAS_JUST: equ 40h ;Op amp bias level justified
0002 REF_MUX: equ 2h ;Ref mux setting
0038 REF_MUX_MASK: equ 38h ;Ref mux setting mask
0010 REF_MUX_JUST: equ 10h ;Ref mux setting justified
0001 AGND_BYPASS: equ 1h ;AGndBypass setting
0040 AGND_BYPASS_MASK: equ 40h ;AGndBypass setting mask
0040 AGND_BYPASS_JUST: equ 40h ;AGndBypass setting justified
0000 SYSCLK_SOURCE: equ 0h | 0h ;SysClk Source setting
0006 SYSCLK_SOURCE_MASK: equ 4h | 2h ;SysClk Source setting mask
0000 SYSCLK_SOURCE_JUST: equ 0h | 0h ;SysClk Source setting justified
0001 SYSCLK_2_DISABLE: equ 1h ;SysClk*2 Disable setting
0001 SYSCLK_2_DISABLE_MASK: equ 1h ;SysClk*2 Disable setting mask
0001 SYSCLK_2_DISABLE_JUST: equ 1h ;SysClk*2 Disable setting justified
0000 ;
0000 ; register initial values
0000 ;
0029 ANALOG_IO_CONTROL: equ 29h ;Analog IO Control register (ABF_CR)
0000 PORT_0_GLOBAL_SELECT: equ 0h ;Port 0 global select register (PRT0GS)
0000 PORT_0_DRIVE_0: equ 0h ;Port 0 drive mode 0 register (PRT0DM0)
00FF PORT_0_DRIVE_1: equ ffh ;Port 0 drive mode 1 register (PRT0DM1)
00FF PORT_0_DRIVE_2: equ ffh ;Port 0 drive mode 2 register (PRT0DM2)
0000 PORT_0_INTENABLE: equ 0h ;Port 0 interrupt enable register (PRT0IE)
0000 PORT_0_INTCTRL_0: equ 0h ;Port 0 interrupt control 0 register (PRT0IC0)
0000 PORT_0_INTCTRL_1: equ 0h ;Port 0 interrupt control 1 register (PRT0IC1)
0094 PORT_1_GLOBAL_SELECT: equ 94h ;Port 1 global select register (PRT1GS)
00FF PORT_1_DRIVE_0: equ ffh ;Port 1 drive mode 0 register (PRT1DM0)
0000 PORT_1_DRIVE_1: equ 0h ;Port 1 drive mode 1 register (PRT1DM1)
0000 PORT_1_DRIVE_2: equ 0h ;Port 1 drive mode 2 register (PRT1DM2)
0000 PORT_1_INTENABLE: equ 0h ;Port 1 interrupt enable register (PRT1IE)
0000 PORT_1_INTCTRL_0: equ 0h ;Port 1 interrupt control 0 register (PRT1IC0)
0000 PORT_1_INTCTRL_1: equ 0h ;Port 1 interrupt control 1 register (PRT1IC1)
0002 PORT_2_GLOBAL_SELECT: equ 2h ;Port 2 global select register (PRT2GS)
002A PORT_2_DRIVE_0: equ 2ah ;Port 2 drive mode 0 register (PRT2DM0)
00FD PORT_2_DRIVE_1: equ fdh ;Port 2 drive mode 1 register (PRT2DM1)
00D5 PORT_2_DRIVE_2: equ d5h ;Port 2 drive mode 2 register (PRT2DM2)
0000 PORT_2_INTENABLE: equ 0h ;Port 2 interrupt enable register (PRT2IE)
0000 PORT_2_INTCTRL_0: equ 0h ;Port 2 interrupt control 0 register (PRT2IC0)
0000 PORT_2_INTCTRL_1: equ 0h ;Port 2 interrupt control 1 register (PRT2IC1)
0000 PORT_3_GLOBAL_SELECT: equ 0h ;Port 3 global select register (PRT3GS)
0000 PORT_3_DRIVE_0: equ 0h ;Port 3 drive mode 0 register (PRT3DM0)
0000 PORT_3_DRIVE_1: equ 0h ;Port 3 drive mode 1 register (PRT3DM1)
0000 PORT_3_DRIVE_2: equ 0h ;Port 3 drive mode 2 register (PRT3DM2)
0000 PORT_3_INTENABLE: equ 0h ;Port 3 interrupt enable register (PRT3IE)
0000 PORT_3_INTCTRL_0: equ 0h ;Port 3 interrupt control 0 register (PRT3IC0)
0000 PORT_3_INTCTRL_1: equ 0h ;Port 3 interrupt control 1 register (PRT3IC1)
0000 PORT_4_GLOBAL_SELECT: equ 0h ;Port 4 global select register (PRT4GS)
0000 PORT_4_DRIVE_0: equ 0h ;Port 4 drive mode 0 register (PRT4DM0)
0000 PORT_4_DRIVE_1: equ 0h ;Port 4 drive mode 1 register (PRT4DM1)
0000 PORT_4_DRIVE_2: equ 0h ;Port 4 drive mode 2 register (PRT4DM2)
0000 PORT_4_INTENABLE: equ 0h ;Port 4 interrupt enable register (PRT4IE)
0000 PORT_4_INTCTRL_0: equ 0h ;Port 4 interrupt control 0 register (PRT4IC0)
0000 PORT_4_INTCTRL_1: equ 0h ;Port 4 interrupt control 1 register (PRT4IC1)
0000 PORT_5_GLOBAL_SELECT: equ 0h ;Port 5 global select register (PRT5GS)
0000 PORT_5_DRIVE_0: equ 0h ;Port 5 drive mode 0 register (PRT5DM0)
0000 PORT_5_DRIVE_1: equ 0h ;Port 5 drive mode 1 register (PRT5DM1)
0000 PORT_5_DRIVE_2: equ 0h ;Port 5 drive mode 2 register (PRT5DM2)
0000 PORT_5_INTENABLE: equ 0h ;Port 5 interrupt enable register (PRT5IE)
0000 PORT_5_INTCTRL_0: equ 0h ;Port 5 interrupt control 0 register (PRT5IC0)
0000 PORT_5_INTCTRL_1: equ 0h ;Port 5 interrupt control 1 register (PRT5IC1)
0000
export LoadConfigInit
export _LoadConfigInit
export LoadConfig_pulserate
export _LoadConfig_pulserate
export NO_SHADOW
export _NO_SHADOW
0010 FLAG_CFG_MASK: equ 10h ;M8C flag register REG address bit mask
00FF END_CONFIG_TABLE: equ ffh ;end of config table indicator
0000
AREA psoc_config(rom, rel)
0000 _LoadConfigInit:
0000 LoadConfigInit:
0000
0000 7C0000 lcall LoadConfigTBL_pulserate_Ordered
0003 7C0007 lcall LoadConfig_pulserate
0006
0006 7F ret
0007
0007 ;
0007 ; Load Configuration pulserate
0007 ;
0007 _LoadConfig_pulserate:
0007 LoadConfig_pulserate:
0007 08 push a
0008 10 push x
0009 70EF and F, ~FLAG_XIO_MASK
000B 5000 mov a, 0
000D 67 asr a
000E 5000 mov A, >LoadConfigTBL_pulserate_Bank0 ;load bank 0 table
0010 5700 mov X, <LoadConfigTBL_pulserate_Bank0
0012 7C0026 lcall LoadConfig ;load the bank 0 values
0015 7110 or F, FLAG_XIO_MASK
0017 5001 mov a, 1
0019 67 asr a
001A 5000 mov A, >LoadConfigTBL_pulserate_Bank1 ;load bank 1 table
001C 5700 mov X, <LoadConfigTBL_pulserate_Bank1
001E 7C0026 lcall LoadConfig ;load the bank 1 values
0021 70EF and F, ~FLAG_XIO_MASK
0023 20 pop x
0024 18 pop a
0025 7F ret
0026
0026
0026 ;
0026 ; LoadConfig
0026 ;
0026 ; This function is not exported. It assumes that the address of the table
0026 ; to be loaded is contained in the X and A registers as if a romx instruction
0026 ; is the next instruction to be executed, i.e. lower address in X and uppper
0026 ; address in A. There is no return value.
0026 ;
0026 LoadConfig:
0026 3802 add SP, 2 ;set up temp vars
0028 10 push X
0029 08 push A
002A 4F mov X, SP
002B 56FC00 mov [X-4], 0
002E D004 jnc LoadBank0Setup
0030 56FC01 mov [X-4], 1
0033 LoadBank0Setup:
0033 18 pop A
0034 20 pop X
0035 LoadConfigLp:
0035 10 push X ;save config table address on stack
0036 08 push A
0037 70EF and F, ~FLAG_XIO_MASK
0039 62E300 mov reg[RES_WDT], 00h
003C 4F mov X, SP ;check for bank 1 load
003D 48FC01 tst [X-4], 1
0040 A003 jz LoadingBank0
0042 7110 or F, FLAG_XIO_MASK
0044 LoadingBank0:
0044 18 pop A
0045 20 pop X
0046 10 push X
0047 08 push A
0048 28 romx ;load config address
0049 39FF cmp A, END_CONFIG_TABLE ;check for end of table
004B A01A jz EndLoadConfig ;if so, end of load
004D 4F mov X, SP ;save the address away
004E 54FD mov [X-3], A
0050 18 pop A ;retrieve the table address
0051 20 pop X
0052 75 inc X ;advance to the data byte
0053 D002 jnc NoOverFlow1 ;check for overflow
0055 74 inc A ;if so, increment MSB
0056 NoOverFlow1:
0056 10 push X ;save the config table address again
0057 08 push A
0058 28 romx ;load the config data
0059 4F mov X, SP ;retrieve the config address
005A 59FD mov X, [X-3]
005C 6100 mov reg[X], A ;write the config data
005E 18 pop A ;retrieve the table address
005F 20 pop X
0060 75 inc X ;advance to the next address
0061 D002 jnc NoOverFlow2 ;check for overflow
0063 74 inc A ;if so, increment MSB
0064 NoOverFlow2:
0064 8FD0 jmp LoadConfigLp ;loop back
0066 EndLoadConfig:
0066 18 pop A ;clean up the stack
0067 20 pop X
0068 38FE add SP, -2
006A 7F ret
006B
AREA virtual_registers(ram, rel)
0000 NO_SHADOW:
0000 _NO_SHADOW:
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