📄 adc.lis
字号:
0014 _ADC_GetSamples:
0014
0014 5300 mov [ADC_bSampC], A ; Store sample count
0016
0016 902D call ADC_StopAD ; Halt PWM and counter, Disable
0018 ; Interrupts, Put A/D in reset
0018
0018 492AFF tst reg[ADC_bPWM_IntTime_MSB], ffh ; Check to see if upper PWM is zero
001B B005 jnz ADC_LoadMSBCounter
001D
001D 500D mov A,ADC_bNUMBITS ; Resolution has not been set yet - get and set the resolution
001F 904A call ADC_SetResolution
0021
0021 ADC_LoadMSBCounter: ; The PWM has been setup by SetResolution, now set the upper
0021 ; counter which will be the same as the period.
0021 ; Reset MSB of counter to most negative value
0021
0021 5D2A mov A,reg[ADC_bPWM_IntTime_MSB] ; Get MSB of PWM and move it into RAM
0023 5300 mov [ADC_cCounterU], A ; Use counter as temp location
0025 5000 mov A, 00h ; Load A with zero for the calculation
0027 1200 sub A, [ADC_cCounterU] ; 0 - MSB_PWM = MSB_of_most_neg_value
0029 67 asr A ; Half the range (+ and -)
IF (ADC_DATA_FORMAT)
mov [ADC_cCounterU], A ; Place result back into MSB of counter
ELSE
002A 550000 mov [ADC_cCounterU], 00h ; Always start at zero for unsigned values
ENDIF
002D 5D26 mov A, reg[ADC_bPWM_IntTime_LSB] ; Dummy Read - required do not remove
002F 622DFF mov reg[ADC_bPeriod], FFh ; Make sure counter starts at FF
0032
0032 4187EF and reg[ADC_bfAtoDcr3],~ADC_fFSW0 ; Take Integrator out of reset
IF ADC_NoAZ
0035 4186DF and reg[ADC_bfAtoDcr2],~ADC_fAutoZero ; Take Integrator out of AutoZero
ENDIF
; Enable the A/D and Start it!
0038 432F05 or reg[ADC_bCounter_CR0], (ADC_fDBLK_ENABLE|ADC_fPULSE_WIDE) ; Enable the Counter
003B 432701 or reg[ADC_fPWM_LSB_CR0], ADC_fDBLK_ENABLE ; Enable PWM
003E 43E104 or reg[ADC_bfPWM16_INT_REG], ADC_bfPWM16_Mask ; Enable Counter interrupts
0041 43E108 or reg[ADC_bfCounter_INT_REG], ADC_bfCounter_Mask
0044
0044 7F ret
0045 .ENDSECTION
0045
0045 .SECTION
0045 ;-----------------------------------------------------------------------------
0045 ; FUNCTION NAME: ADC_StopAD
0045 ;
0045 ; DESCRIPTION:
0045 ; Completely shuts down the A/D is an orderly manner. Both the
0045 ; Timer and Counter are disabled and their interrupts are deactivated.
0045 ;
0045 ;-----------------------------------------------------------------------------
0045 ;
0045 ; ARGUMENTS: None
0045 ;
0045 ; RETURNS: NA
0045 ;
0045 ; SIDE EFFECTS:
0045 ; REGISTERS ARE VOLATILE: THE A AND X REGISTERS MAY BE MODIFIED!
0045 ;
0045 ; THEORY of OPERATION or PROCEDURE:
0045 ;
0045 ;-----------------------------------------------------------------------------
0045 ADC_StopAD:
0045 _ADC_StopAD:
0045
0045 4127FE and reg[ADC_fPWM_LSB_CR0], ~ADC_fDBLK_ENABLE ; Disable the PWM
0048
0048 412FFE and reg[ADC_bCounter_CR0], ~ADC_fDBLK_ENABLE ; Disable the Counter
004B
IF ADC_NoAZ
004B 438620 or reg[ADC_bfAtoDcr2], ADC_fAutoZero ; Put the Integrator into Autozero mode
ENDIF
004E 438710 or reg[ADC_bfAtoDcr3], ADC_fFSW0 ; Put Integrator into reset
0051 08 push A
0052 41E1FB and reg[ADC_bfPWM16_INT_REG], ~ADC_bfPWM16_Mask ; disable specified interrupt enable bit
0055 41E1F7 and reg[ADC_bfCounter_INT_REG], ~ADC_bfCounter_Mask ; disable specified interrupt enable bit
0058 18 pop A
0059
0059 7F ret
005A .ENDSECTION
005A
005A .SECTION
005A ;-----------------------------------------------------------------------------
005A ; FUNCTION NAME: ADC_fIsData
005A ; FUNCTION NAME: ADC_fIsDataAvailable
005A ;
005A ; DESCRIPTION:
005A ; Returns the status of the A/D Data is set whenever a new data
005A ; value is available.
005A ;
005A ;-----------------------------------------------------------------------------
005A ;
005A ; ARGUMENTS: None
005A ;
005A ; RETURNS:
005A ; A Returns data status A == 0 no data available
005A ; A != 0 data available
005A ;
005A ; SIDE EFFECTS:
005A ; REGISTERS ARE VOLATILE: THE A AND X REGISTERS MAY BE MODIFIED!
005A ;
005A ; THEORY of OPERATION or PROCEDURE:
005A ;
005A ;-----------------------------------------------------------------------------
005A ADC_fIsData:
005A _ADC_fIsData:
005A ADC_fIsDataAvailable:
005A _ADC_fIsDataAvailable:
005A 5100 mov A, [ADC_bfStatus] ; Get status byte
005C 2110 and A, ADC_fDATA_READY ; Mask off other bits
005E 7F ret
005F .ENDSECTION
005F
005F .SECTION
005F ;-----------------------------------------------------------------------------
005F ; FUNCTION NAME: ADC_iGetDataClearFlag
005F ; FUNCTION NAME: ADC_iGetData
005F ;
005F ; DESCRIPTION:
005F ; Returns the data from the A/D. Does not check if data is available.
005F ; iGetDataClearFlag clears the result ready flag as well.
005F ;
005F ;-----------------------------------------------------------------------------
005F ;
005F ; ARGUMENTS: None
005F ;
005F ; RETURNS:
005F ; A:X return the ADC result.
005F ;
005F ; SIDE EFFECTS:
005F ; REGISTERS ARE VOLATILE: THE A AND X REGISTERS MAY BE MODIFIED!
005F ;
005F ; THEORY of OPERATION or PROCEDURE:
005F ;
005F ;-----------------------------------------------------------------------------
005F ADC_iGetDataClearFlag:
005F _ADC_iGetDataClearFlag:
005F 2600EF and [ADC_bfStatus], ~ADC_fDATA_READY ; Clear Data ready bit
0062
0062 ADC_iGetData:
0062 _ADC_iGetData:
0062 5800 mov X, [(ADC_iResult + HighByte)]
0064 5101 mov A, [(ADC_iResult + LowByte)]
0066 7F ret
0067 .ENDSECTION
0067
0067 .SECTION
0067 ;-----------------------------------------------------------------------------
0067 ; FUNCTION NAME: ADC_ClearFlag
0067 ;
0067 ; DESCRIPTION:
0067 ; Clears the data ready flag.
0067 ;
0067 ;-----------------------------------------------------------------------------
0067 ;
0067 ; ARGUMENTS: None
0067 ;
0067 ; RETURNS: NA
0067 ;
0067 ; SIDE EFFECTS:
0067 ; REGISTERS ARE VOLATILE: THE A AND X REGISTERS MAY BE MODIFIED!
0067 ;
0067 ; THEORY of OPERATION or PROCEDURE:
0067 ;
0067 ;-----------------------------------------------------------------------------
0067
0067 ADC_ClearFlag:
0067 _ADC_ClearFlag:
0067 2600EF and [ADC_bfStatus], ~ADC_fDATA_READY ; Clear Data ready bit
006A 7F ret
006B .ENDSECTION
006B
006B .SECTION
006B ;-----------------------------------------------------------------------------
006B ; FUNCTION NAME: ADC_SetResolution
006B ;
006B ; DESCRIPTION:
006B ; Sets A/D resolution between 7 and 13 bits.
006B ;
006B ;-----------------------------------------------------------------------------
006B ;
006B ; ARGUMENTS:
006B ; A Passes the number of bits of resolution, between 7 and 13.
006B ;
006B ; RETURNS: NA
006B ;
006B ; SIDE EFFECTS:
006B ; REGISTERS ARE VOLATILE: THE A AND X REGISTERS MAY BE MODIFIED!
006B ; This function halts the PWM and the counter to sync the A/D , but
006B ; does not re-enable the counter or PWM. To restart the A/D, "Get_Samples"
006B ; should be called.
006B ;
006B ; THEORY of OPERATION or PROCEDURE:
006B ;
006B ;-----------------------------------------------------------------------------
006B ADC_SetResolution:
006B _ADC_SetResolution:
006B
006B 9FD8 call ADC_StopAD ; Stop the A/D if it is running
006D 550000 mov [ADC_bfStatus], 00h ⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -