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00E1 OSC_CR1: equ E1h ; System VC1/VC2 Divider Control Register (RW)
00F0 OSC_CR1_VC1: equ F0h ; MASK: System VC1 24MHz/External Clk divider
000F OSC_CR1_VC2: equ 0Fh ; MASK: System VC2 24MHz/External Clk divider
0000
00E2 OSC_CR2: equ E2h ; Oscillator Control Register 2 (RW)
0004 OSC_CR2_EXTCLKEN: equ 04h ; MASK: Enable/Disable External Clock
0002 OSC_CR2_IMODIS: equ 02h ; MASK: Enable/Disable System (IMO) Clock Net
0001 OSC_CR2_SYSCLKX2DIS: equ 01h ; MASK: Enable/Disable 48MHz clock source
0000
00E3 VLT_CR: equ E3h ; Voltage Monitor Control Register (RW)
0080 VLT_CR_SMP: equ 80h ; MASK: Enable Switch Mode Pump
0030 VLT_CR_PORLEV: equ 30h ; MASK: Mask for Power on Reset level control
0000 VLT_CR_3V0_POR: equ 00h ; MASK: Set the Precision POR to 3.0V
0010 VLT_CR_4V5_POR: equ 10h ; MASK: Set the Precision POR to 4.5V
0020 VLT_CR_4V75_POR: equ 20h ; MASK: Set the Precision POR to 4.75V
0030 VLT_CR_DISABLE: equ 30h ; MASK: Disable the Precision POR
0008 VLT_CR_LVDTBEN: equ 08h ; MASK: Enable the CPU Throttle Back on LVD
0007 VLT_CR_VM: equ 07h ; MASK: Mask for Voltage Monitor level setting
0000
00E4 VLT_CMP: equ E4h ; Voltage Monitor Comparators Register (R)
0008 VLT_CMP_PUMP: equ 08h ; MASK: Vcc below SMP trip level
0008 VLT_CMP_LVD: equ 08h ; MASK: Vcc below LVD trip level
0008 VLT_CMP_PPOR: equ 08h ; MASK: Vcc below PPOR trip level
0000
00E8 IMO_TR: equ E8h ; Internal Main Oscillator Trim Register (W)
00E9 ILO_TR: equ E9h ; Internal Low-speed Oscillator Trim (W)
00EA BDG_TR: equ EAh ; Band Gap Trim Register (W)
00EB ECO_TR: equ EBh ; External Oscillator Trim Register (W)
0000
0000 ;;=============================================================================
0000 ;; M8C System Macros
0000 ;; These macros should be used when their functions are needed.
0000 ;;=============================================================================
0000
0000 ;----------------------------------------------------
0000 ; Swapping Register Banks
0000 ;----------------------------------------------------
0000 macro M8C_SetBank0
0000 and F, ~FLAG_XIO_MASK
0000 macro M8C_SetBank1
0000 or F, FLAG_XIO_MASK
0000 macro M8C_EnableGInt
0000 or F, FLAG_GLOBAL_IE
0000 macro M8C_DisableGInt
0000 and F, ~FLAG_GLOBAL_IE
0000 macro M8C_DisableIntMask
0000 and reg[@0], ~@1 ; disable specified interrupt enable bit
0000 macro M8C_EnableIntMask
0000 or reg[@0], @1 ; enable specified interrupt enable bit
0000 macro M8C_ClearIntFlag
0000 and reg[@0], ~@1 ; clear specified interrupt enable bit
0000 macro M8C_EnableWatchDog
0000 and reg[CPU_SCR0], ~CPU_SCR0_PORS_MASK
0000 macro M8C_ClearWDT
0000 mov reg[RES_WDT], 00h
0000 macro M8C_ClearWDTAndSleep
0000 mov reg[RES_WDT], 38h
0000 macro M8C_Stall
0000 or reg[ASY_CR], ASY_CR_SYNCEN
0000 macro M8C_Unstall
0000 and reg[ASY_CR], ~ASY_CR_SYNCEN
0000 macro M8C_Sleep
0000 or reg[CPU_SCR0], CPU_SCR0_SLEEP_MASK
0000 ; The next instruction to be executed depends on the state of the
0000 ; various interrupt enable bits. If some interrupts are enabled
0000 ; and the global interrupts are disabled, the next instruction will
0000 ; be the one that follows the invocation of this macro. If global
0000 ; interrupts are also enabled then the next instruction will be
0000 ; from the interrupt vector table. If no interrupts are enabled
0000 ; then the CPU sleeps forever.
0000 macro M8C_Stop
0000 ; In general, you probably don't want to do this, but here's how:
0000 or reg[CPU_SCR0], CPU_SCR0_STOP_MASK
0000 ; Next instruction to be executed is located in the interrupt
0000 ; vector table entry for Power-On Reset.
0000 macro M8C_Reset
0000 ; Restore CPU to the power-on reset state.
0000 mov A, 0
0000 SSC
0000 ; Next non-supervisor instruction will be at interrupt vector 0.
0000 macro Suspend_CodeCompressor
0000 or F, 0
0000 macro Resume_CodeCompressor
0000 add SP, 0
export ADC_Start
export _ADC_Start
export ADC_SetPower
export _ADC_SetPower
export ADC_Stop
export _ADC_Stop
export ADC_GetSamples
export _ADC_GetSamples
export ADC_StopAD
export _ADC_StopAD
export ADC_fIsData
export _ADC_fIsData
export ADC_fIsDataAvailable
export _ADC_fIsDataAvailable
export ADC_iGetData
export _ADC_iGetData
export ADC_ClearFlag
export _ADC_ClearFlag
export ADC_iGetDataClearFlag
export _ADC_iGetDataClearFlag
export ADC_SetResolution
export _ADC_SetResolution
;-----------------------------------------------
; EQUATES
;-----------------------------------------------
0001 LowByte: equ 1
0000 HighByte: equ 0
0000
0000 ; Calctime parameters
00C8 wCalcTime: equ ADC_bCALCTIME
0000
AREA UserModules (ROM, REL)
0000 .SECTION
0000 ;-----------------------------------------------------------------------------
0000 ; FUNCTION NAME: ADC_Start
0000 ; FUNCTION NAME: ADC_SetPower
0000 ;
0000 ; DESCRIPTION:
0000 ; Applies power setting to the module's analog PSoc block.
0000 ;
0000 ;-----------------------------------------------------------------------------
0000 ;
0000 ; ARGUMENTS:
0000 ; A Contains power level setting 0 to 3
0000 ;
0000 ; RETURNS: NA
0000 ;
0000 ; SIDE EFFECTS:
0000 ; REGISTERS ARE VOLATILE: THE A AND X REGISTERS MAY BE MODIFIED!
0000 ;
0000 ; THEORY of OPERATION or PROCEDURE:
0000 ;
0000 ;-----------------------------------------------------------------------------
0000 ADC_Start:
0000 _ADC_Start:
0000 ADC_SetPower:
0000 _ADC_SetPower:
0000 2103 and A,ADC_bfPOWERMASK ; Mask only the valid power setting bits
0002 4F mov X, SP ; Get location of next location on stack
0003 08 push A ; Save power value on temp location
0004 5D87 mov A, reg[ADC_bfAtoDcr3] ; Get current value of AtoDcr3
0006 21FC and A, ~ADC_bfPOWERMASK ; Mask off old power value
0008 2B00 or A, [X] ; OR in new power value
000A 29F0 or A, f0h ; Make sure other register is set correctly
000C 6087 mov reg[ADC_bfAtoDcr3], A ; Reload CR with new power value
000E 18 pop A ; Restore the stack and power value
000F 7F ret
0010 .ENDSECTION
0010
0010 .SECTION
0010 ;-----------------------------------------------------------------------------
0010 ; FUNCTION NAME: ADC_Stop
0010 ;
0010 ; DESCRIPTION:
0010 ; Removes power from the module's analog PSoc block, but the digital
0010 ; blocks keep on running.
0010 ;
0010 ;-----------------------------------------------------------------------------
0010 ;
0010 ; ARGUMENTS: None
0010 ;
0010 ; RETURNS: NA
0010 ;
0010 ; SIDE EFFECTS:
0010 ; REGISTERS ARE VOLATILE: THE A AND X REGISTERS MAY BE MODIFIED!
0010 ;
0010 ; THEORY of OPERATION or PROCEDURE:
0010 ;
0010 ;-----------------------------------------------------------------------------
0010 ADC_Stop:
0010 _ADC_Stop:
0010 4187FC and reg[ADC_bfAtoDcr3], ~ADC_bfPOWERMASK
0013 7F ret
0014 .ENDSECTION
0014
0014 .SECTION
0014 ;-----------------------------------------------------------------------------
0014 ; FUNCTION NAME: ADC_Get_Samples
0014 ;
0014 ; DESCRIPTION:
0014 ; Starts the A/D convertor and will place data is memory. A flag
0014 ; is set whenever a new data value is available.
0014 ;
0014 ;-----------------------------------------------------------------------------
0014 ;
0014 ; ARGUMENTS:
0014 ; A Number of samples to be taken. A zero will cause the ADC to run
0014 ; continuously.
0014 ;
0014 ; RETURNS: NA
0014 ;
0014 ; SIDE EFFECTS:
0014 ; REGISTERS ARE VOLATILE: THE A AND X REGISTERS MAY BE MODIFIED!
0014 ;
0014 ; THEORY of OPERATION or PROCEDURE:
0014 ;
0014 ;-----------------------------------------------------------------------------
0014 ADC_GetSamples:
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