📄 adc.lis
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0000 ;;*****************************************************************************
0000 ;;*****************************************************************************
0000 ;; ADC.asm
0000 ;; Version: 2.1, Updated on 2003/11/18 at 14:58:51
0000 ;; Generated by PSoC Designer ver 4.1 BETA b923 : 11 December, 2003
0000 ;;
0000 ;; DESCRIPTION: ADCINCVR User Module software implementation file for the
0000 ;; 22/24/25/26/27xxx PSoC family of devices.
0000 ;;
0000 ;; NOTE: User Module APIs conform to the fastcall convention for marshalling
0000 ;; arguments and observe the associated "Registers are volatile" policy.
0000 ;; This means it is the caller's responsibility to preserve any values
0000 ;; in the X and A registers that are still needed after the API
0000 ;; function returns. Even though these registers may be preserved now,
0000 ;; there is no guarantee they will be preserved in future releases.
0000 ;;-----------------------------------------------------------------------------
0000 ;; Copyright (c) Cypress MicroSystems 2001-2003. All Rights Reserved.
0000 ;;*****************************************************************************
0000 ;;*****************************************************************************
0000
0008 ADC_bfCounter_Mask: equ 08h
00E1 ADC_bfCounter_INT_REG: equ 0e1h
0000
0000 ; PWM Constants
0004 ADC_bfPWM16_Mask: equ 04h
00E1 ADC_bfPWM16_INT_REG: equ 0e1h
0000
0000 ; Power Settings
0003 ADC_bfPOWERMASK: equ 03h
0000 ADC_OFF: equ 00h
0001 ADC_LOWPOWER: equ 01h
0002 ADC_MEDPOWER: equ 02h
0003 ADC_HIGHPOWER: equ 03h
0000
0000 ; Parameter Settings
000D ADC_bNUMBITS: equ dh
00C8 ADC_bCALCTIME: equ c8h
000D ADC_bMAXRES: equ 0Dh ; Max resolution 13 bits
0007 ADC_bMINRES: equ 07h ; Min resolution 7 bits
0008 ADC_fCOMPARE_TRUE: equ 08h ; Bit to enable compare True interrupts
0000
0000 ; Functionality constants
0010 ADC_fFSW0: equ 10h ; Switch Cap FSW0 switch enable
0001 ADC_NoAZ: equ 01h ; Set if AutoZero is not enabled
0020 ADC_fAutoZero: equ 20h ; Switch Cap AutoZero switch enable
0001 ADC_fDBLK_ENABLE: equ 01h ; Digital block enable bit
0004 ADC_fPULSE_WIDE: equ 04h ; Enable wide terminal count pulse.
0000
0000 ; fStatus definitions
0010 ADC_fDATA_READY: equ 10h ; This bit is set when data is available
000F ADC_bRES_MASK: equ 0Fh ; This bit while in integrate cycle
0000
0000 ; Data Format
0000 ADC_DATA_FORMAT: equ 0
0000
0000
0000 ;--------------------------------------------------
0000 ; Registers used by ADC
0000 ;--------------------------------------------------
0000 ; ADCINCVR PSoC Block register Definitions
0000 ; Integrator Block Register Definitions
0084 ADC_bfAtoDcr0: equ 84h
0085 ADC_bfAtoDcr1: equ 85h
0086 ADC_bfAtoDcr2: equ 86h
0087 ADC_bfAtoDcr3: equ 87h
0000
0000 ; Counter Block Register Definitions
002C ADC_fCounterFN: equ 2ch
002D ADC_fCounterSL: equ 2dh
002E ADC_fCounterOS: equ 2eh
002C ADC_bCount: equ 2ch
002D ADC_bPeriod: equ 2dh
002E ADC_bCompare: equ 2eh
002F ADC_bCounter_CR0: equ 2fh
0000
0000 ; PWM16 Block Register Definitions
0024 ADC_bfPWM_LSB_FN: equ 24h
0028 ADC_bfPWM_MSB_FN: equ 28h
0027 ADC_fPWM_LSB_CR0: equ 27h
002B ADC_fPWM_MSB_CR0: equ 2bh
0028 ADC_bPWM_Count_MSB: equ 28h
0024 ADC_bPWM_Count_LSB: equ 24h
0029 ADC_bPWM_Period_MSB: equ 29h
0025 ADC_bPWM_Period_LSB: equ 25h
002A ADC_bPWM_IntTime_MSB: equ 2ah
0026 ADC_bPWM_IntTime_LSB: equ 26h
0024 ADC_bfPWM_LSB_FN: equ 24h
0028 ADC_bfPWM_MSB_FN: equ 28h
0000
0000
0000 ; End of File ADC.inc
0000
0000
0010 FLAG_XIO_MASK: equ 10h
0008 FLAG_SUPER: equ 08h
0004 FLAG_CARRY: equ 04h
0002 FLAG_ZERO: equ 02h
0001 FLAG_GLOBAL_IE: equ 01h
0000
0000
0000 ;;=============================================================================
0000 ;; Register Space, Bank 0
0000 ;;=============================================================================
0000
0000 ;------------------------------------------------
0000 ; Port Registers
0000 ; Note: Also see this address range in Bank 1.
0000 ;------------------------------------------------
0000 ; Port 0
0000 PRT0DR: equ 00h ; Port 0 Data Register (RW)
0001 PRT0IE: equ 01h ; Port 0 Interrupt Enable Register (RW)
0002 PRT0GS: equ 02h ; Port 0 Global Select Register (RW)
0003 PRT0DM2: equ 03h ; Port 0 Drive Mode 2 (RW)
0000 ; Port 1
0004 PRT1DR: equ 04h ; Port 1 Data Register (RW)
0005 PRT1IE: equ 05h ; Port 1 Interrupt Enable Register (RW)
0006 PRT1GS: equ 06h ; Port 1 Global Select Register (RW)
0007 PRT1DM2: equ 07h ; Port 1 Drive Mode 2 (RW)
0000 ; Port 2
0008 PRT2DR: equ 08h ; Port 2 Data Register (RW)
0009 PRT2IE: equ 09h ; Port 2 Interrupt Enable Register (RW)
000A PRT2GS: equ 0Ah ; Port 2 Global Select Register (RW)
000B PRT2DM2: equ 0Bh ; Port 2 Drive Mode 2 (RW)
0000 ; Port 3
000C PRT3DR: equ 0Ch ; Port 3 Data Register (RW)
000D PRT3IE: equ 0Dh ; Port 3 Interrupt Enable Register (RW)
000E PRT3GS: equ 0Eh ; Port 3 Global Select Register (RW)
000F PRT3DM2: equ 0Fh ; Port 3 Drive Mode 2 (RW)
0000 ; Port 4
0010 PRT4DR: equ 10h ; Port 4 Data Register (RW)
0011 PRT4IE: equ 11h ; Port 4 Interrupt Enable Register (RW)
0012 PRT4GS: equ 12h ; Port 4 Global Select Register (RW)
0013 PRT4DM2: equ 13h ; Port 4 Drive Mode 2 (RW)
0000 ; Port 5
0014 PRT5DR: equ 14h ; Port 5 Data Register (RW)
0015 PRT5IE: equ 15h ; Port 5 Interrupt Enable Register (RW)
0016 PRT5GS: equ 16h ; Port 5 Global Select Register (RW)
0017 PRT5DM2: equ 17h ; Port 5 Drive Mode 2 (RW)
0000
0000 ;------------------------------------------------
0000 ; Digital PSoC(tm) block Registers
0000 ; Note: Also see this address range in Bank 1.
0000 ;------------------------------------------------
0000 ; Digital PSoC block 00, Basic Type B
0020 DBB00DR0: equ 20h ; data register 0 (#)
0021 DBB00DR1: equ 21h ; data register 1 (W)
0022 DBB00DR2: equ 22h ; data register 2 (RW)
0023 DBB00CR0: equ 23h ; control & status register 0 (#)
0000
0000 ; Digital PSoC block 01, Basic Type B
0024 DBB01DR0: equ 24h ; data register 0 (#)
0025 DBB01DR1: equ 25h ; data register 1 (W)
0026 DBB01DR2: equ 26h ; data register 2 (RW)
0027 DBB01CR0: equ 27h ; control & status register 0 (#)
0000
0000 ; Digital PSoC block 02, Communications Type B
0028 DCB02DR0: equ 28h ; data register 0 (#)
0029 DCB02DR1: equ 29h ; data register 1 (W)
002A DCB02DR2: equ 2Ah ; data register 2 (RW)
002B DCB02CR0: equ 2Bh ; control & status register 0 (#)
0000
0000 ; Digital PSoC block 03, Communications Type B
002C DCB03DR0: equ 2Ch ; data register 0 (#)
002D DCB03DR1: equ 2Dh ; data register 1 (W)
002E DCB03DR2: equ 2Eh ; data register 2 (RW)
002F DCB03CR0: equ 2Fh ; control & status register 0 (#)
0000
0000 ; Digital PSoC block 10, Basic Type B
0030 DBB10DR0: equ 30h ; data register 0 (#)
0031 DBB10DR1: equ 31h ; data register 1 (W)
0032 DBB10DR2: equ 32h ; data register 2 (RW)
0033 DBB10CR0: equ 33h ; control & status register 0 (#)
0000
0000 ; Digital PSoC block 11, Basic Type B
0034 DBB11DR0: equ 34h ; data register 0 (#)
0035 DBB11DR1: equ 35h ; data register 1 (W)
0036 DBB11DR2: equ 36h ; data register 2 (RW)
0037 DBB11CR0: equ 37h ; control & status register 0 (#)
0000
0000 ; Digital PSoC block 12, Communications Type B
0038 DCB12DR0: equ 38h ; data register 0 (#)
0039 DCB12DR1: equ 39h ; data register 1 (W)
003A DCB12DR2: equ 3Ah ; data register 2 (RW)
003B DCB12CR0: equ 3Bh ; control & status register 0 (#)
0000
0000 ; Digital PSoC block 13, Communications Type B
003C DCB13DR0: equ 3Ch ; data register 0 (#)
003D DCB13DR1: equ 3Dh ; data register 1 (W)
003E DCB13DR2: equ 3Eh ; data register 2 (RW)
003F DCB13CR0: equ 3Fh ; control & status register 0 (#)
0000
0000 ;-------------------------------------
0000 ; Analog Resource Control Registers
0000 ;-------------------------------------
0060 AMX_IN: equ 60h ; Analog Input Multiplexor Control (RW)
00C0 AMX_IN_ACI3: equ C0h ; MASK: column 3 input mux
0030 AMX_IN_ACI2: equ 30h ; MASK: column 2 input mux
000C AMX_IN_ACI1: equ 0Ch ; MASK: column 1 input mux
0003 AMX_IN_ACI0: equ 03h ; MASK: column 0 input mux
0000
0063 ARF_CR: equ 63h ; Analog Reference Control Register (RW)
0040 ARF_CR_HBE: equ 40h ; MASK: Bias level control
0038 ARF_CR_REF: equ 38h ; MASK: Analog Reference controls
0007 ARF_CR_REFPWR: equ 07h ; MASK: Analog Reference power
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