📄 os_cpu_a.asm
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BNE OS_CPU_ARM_ExceptHndlr_BreakNothing
; HANDLE NESTING COUNTER:
LDR R3, ?OS_IntNesting ; OSIntNesting++;
LDRB R4, [R3]
ADD R4, R4, #1
STRB R4, [R3]
CMP R4, #1 ; if (OSIntNesting == 1)
BNE OS_CPU_ARM_ExceptHndlr_BreakExcept
;********************************************************************************************************
; EXCEPTION HANDLER: TASK INTERRUPTED
;
; Register Usage: R0 Exception Type
; R1
; R2
; R3
;********************************************************************************************************
OS_CPU_ARM_ExceptHndlr_BreakTask
LDR R3, ?OS_TCBCur ; OSTCBCur->OSTCBStkPtr = SP;
LDR R4, [R3]
STR SP, [R4]
LDR R3, ?OS_CPU_ExceptStkBase ; Switch to exception stack.
LDR SP, [R3]
; EXECUTE EXCEPTION HANDLER:
LDR R1, ?OS_CPU_ExceptHndlr ; OS_CPU_ExceptHndlr(except_type = R0)
MOV LR, PC
BX R1
; Change to SVC mode & disable interruptions.
MSR CPSR_c, #(OS_CPU_ARM_CONTROL_INT_DIS | OS_CPU_ARM_MODE_SVC)
; Call OSIntExit(). This call MAY never return if a ready
; task with higher priority than the interrupted one is
; found.
LDR R0, ?OS_IntExit
MOV LR, PC
BX R0
LDR R3, ?OS_TCBCur ; SP = OSTCBCur->OSTCBStkPtr;
LDR R4, [R3]
LDR SP, [R4]
; RESTORE NEW TASK'S CONTEXT:
LDMFD SP!, {R0} ; Pop new task's CPSR,
MSR SPSR_cxsf, R0
LDMFD SP!, {R0-R12, LR, PC}^ ; Pop new task's context.
;********************************************************************************************************
; EXCEPTION HANDLER: EXCEPTION INTERRUPTED
;
; Register Usage: R0 Exception Type
; R1
; R2
; R3
;********************************************************************************************************
OS_CPU_ARM_ExceptHndlr_BreakExcept
LDR R3, ?OS_CPU_ExceptStkPtr ; OS_CPU_ExceptStkPtr = SP;
STR SP, [R3]
; EXECUTE EXCEPTION HANDLER:
LDR R3, ?OS_CPU_ExceptHndlr ; OS_CPU_ExceptHndlr(except_type = R0)
MOV LR, PC
BX R3
; Change to SVC mode & disable interruptions.
MSR CPSR_c, #(OS_CPU_ARM_CONTROL_INT_DIS | OS_CPU_ARM_MODE_SVC)
; HANDLE NESTING COUNTER:
LDR R3, ?OS_IntNesting ; OSIntNesting--;
LDRB R4, [R3]
SUB R4, R4, #1
STRB R4, [R3]
; RESTORE OLD CONTEXT:
LDMFD SP!, {R0} ; Pop old CPSR,
MSR SPSR_cxsf, R0
LDMFD SP!, {R0-R12, LR, PC}^ ; Pull working registers and return from exception.
;********************************************************************************************************
; EXCEPTION HANDLER: 'NOTHING' INTERRUPTED
;
; Register Usage: R0 Exception Type
; R1
; R2
; R3
;********************************************************************************************************
OS_CPU_ARM_ExceptHndlr_BreakNothing
; EXECUTE EXCEPTION HANDLER:
LDR R3, ?OS_CPU_ExceptHndlr ; OS_CPU_ExceptHndlr(except_type = R0)
MOV LR, PC
BX R3
; Change to SVC mode & disable interruptions.
MSR CPSR_c, #(OS_CPU_ARM_CONTROL_INT_DIS | OS_CPU_ARM_MODE_SVC)
; RESTORE OLD CONTEXT:
LDMFD SP!, {R0} ; Pop old CPSR,
MSR SPSR_cxsf, R0
LDMFD SP!, {R0-R12, LR, PC}^ ; Pull working registers and return from exception.
;********************************************************************************************************
; ENABLE & DISABLE INTERRUPTS
;
; Note(s) : 1) OS_CPU_SR_INT_En() can be called by OS_CPU_ExceptHndlr() AFTER the external
; interrupt source has been cleared. This function will enable IRQs and FIQs so that
; nesting can occur.
;
; 2) OS_CPU_ARM_INT_Dis() can be called to disable IRQs and FIQs so that nesting will not occur.
;********************************************************************************************************
OS_CPU_SR_INT_En
MRS R0, CPSR
BIC R0, R0, #OS_CPU_ARM_CONTROL_INT_DIS ; Clear IRQ and FIQ bits in CPSR to enable all interrupts.
MSR CPSR_c, R0
BX LR
OS_CPU_SR_INT_Dis
MRS R0, CPSR
ORR R0, R0, #OS_CPU_ARM_CONTROL_INT_DIS ; Set IRQ and FIQ bits in CPSR to disable all interrupts.
MSR CPSR_c, R0
BX LR
;********************************************************************************************************
; ENABLE & DISABLE IRQs
;
; Note(s) : 1) OS_CPU_SR_IRQ_En() can be called by OS_CPU_ExceptHndlr() AFTER the external
; interrupt source has been cleared. This function will enable IRQs so that IRQ nesting
; can occur.
;
; 2) OS_CPU_ARM_IRQ_Dis() can be called to disable IRQs so that IRQ nesting will not occur.
;********************************************************************************************************
OS_CPU_SR_IRQ_En
MRS R0, CPSR
BIC R0, R0, #OS_CPU_ARM_CONTROL_IRQ_DIS ; Clear IRQ bit in CPSR to enable IRQs.
MSR CPSR_c, R0
BX LR
OS_CPU_SR_IRQ_Dis
MRS R0, CPSR
ORR R0, R0, #OS_CPU_ARM_CONTROL_IRQ_DIS ; Set IRQ bit in CPSR to disable IRQs.
MSR CPSR_c, R0
BX LR
;********************************************************************************************************
; ENABLE & DISABLE FIQs
;
; Note(s) : 1) OS_CPU_SR_FIQ_En() can be called by OS_CPU_ExceptHndlr() AFTER the external
; interrupt source has been cleared. This function will enable FIQs so that FIQ nesting
; can occur.
;
; 2) OS_CPU_ARM_FIQ_Dis() can be called to disable FIQs so that FIQ nesting will not occur.
;********************************************************************************************************
OS_CPU_SR_FIQ_En
MRS R0, CPSR
BIC R0, R0, #OS_CPU_ARM_CONTROL_FIQ_DIS ; Clear FIQ bit in CPSR to enable FIQs.
MSR CPSR_c, R0
BX LR
OS_CPU_SR_FIQ_Dis
MRS R0, CPSR
ORR R0, R0, #OS_CPU_ARM_CONTROL_FIQ_DIS ; Set FIQ bit in CPSR to disable FIQs.
MSR CPSR_c, R0
BX LR
;*********************************************************************************************************
; POINTERS TO VARIABLES
;*********************************************************************************************************
DATA
?OS_Running:
DC32 OSRunning
?OS_PrioCur:
DC32 OSPrioCur
?OS_PrioHighRdy:
DC32 OSPrioHighRdy
?OS_TCBCur:
DC32 OSTCBCur
?OS_TCBHighRdy:
DC32 OSTCBHighRdy
?OS_IntNesting:
DC32 OSIntNesting
?OS_TaskSwHook:
DC32 OSTaskSwHook
?OS_IntExit:
DC32 OSIntExit
?OS_CPU_ExceptHndlr:
DC32 OS_CPU_ExceptHndlr
?OS_CPU_ExceptStkBase:
DC32 OS_CPU_ExceptStkBase
?OS_CPU_ExceptStkPtr:
DC32 OS_CPU_ExceptStkPtr
END
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