usbf_wb.vhd

USB的 这次 我这只有两个可以上载 谁能告诉我怎么办

-- file usbf_wb
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity usbf_wb is
	generic(usbf_ufc_hadr:integer:=17);
	port
	(
		wb_clk,phy_clk:in std_logic;
		rst			  :in std_logic;
		wb_addr_i	  :in std_logic_vector(usbf_ufc_hadr downto 0);
		wb_data_i	  :in std_logic_vector(31 downto 0);
		wb_data_o	  :buffer std_logic_vector(31 downto 0);
		wb_ack_o	  :buffer std_logic;
		wb_we_i		  :in std_logic;
		wb_stb_i	  :in std_logic;
		wb_cyc_i	  :in std_logic;
		--存储仲裁器
		ma_adr		  :out std_logic_vector(usbf_ufc_hadr downto 0);
		ma_dout		  :out std_logic_vector(31 downto 0);
		ma_din		  :in std_logic_vector(31 downto 0);
		ma_we		  :buffer std_logic;
		ma_req		  :buffer std_logic;
		ma_ack		  :in std_logic;
		--内部积寄存器接口
		rf_re		  :buffer std_logic;
		rf_we		  :out std_logic;
		rf_din		  :in std_logic_vector(31 downto 0);
		rf_dout		  :out std_logic_vector(31 downto 0)
	);
end entity;
architecture arch_usbf_wb of usbf_wb is
constant idle:std_logic_vector(5 downto 0):="000001";
constant ma_wr:std_logic_vector(5 downto 0):="000010";
constant ma_rd:std_logic_vector(5 downto 0):="000100";
constant w0:std_logic_vector(5 downto 0):="001000";
constant w1:std_logic_vector(5 downto 0):="010000";
constant w2:std_logic_vector(5 downto 0):="100000";
signal state,next_state:std_logic_vector(5 downto 0);
signal wb_req_s1: std_logic;
signal wb_ack_d,wb_ack_s1,wb_ack_s1a,wb_ack_s2: std_logic;
signal rf_we_d:std_logic;
begin
--数据、地址由应用模块由驱动，输出至存储器或内部