📄 usbf_mem_arb.map.qmsg
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{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.1 Build 201 11/27/2006 SJ Web Edition " "Info: Version 6.1 Build 201 11/27/2006 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Jul 11 14:22:56 2008 " "Info: Processing started: Fri Jul 11 14:22:56 2008" { } { } 0 0 "Processing started: %1!s!" 0 0} } { } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off usbf_mem_arb -c usbf_mem_arb " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off usbf_mem_arb -c usbf_mem_arb" { } { } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "usbf_mem_arb.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file usbf_mem_arb.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 usbf_mem_arb-arch_of_mem_arb " "Info: Found design unit 1: usbf_mem_arb-arch_of_mem_arb" { } { { "usbf_mem_arb.vhd" "" { Text "C:/Documents and Settings/xiehao/My Documents/my project/FPGA/usb/usbf_mem_arb/usbf_mem_arb.vhd" 31 -1 0 } } } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 usbf_mem_arb " "Info: Found entity 1: usbf_mem_arb" { } { { "usbf_mem_arb.vhd" "" { Text "C:/Documents and Settings/xiehao/My Documents/my project/FPGA/usb/usbf_mem_arb/usbf_mem_arb.vhd" 6 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0} } { } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "usbf_wb.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file usbf_wb.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 usbf_wb-arch_usbf_wb " "Info: Found design unit 1: usbf_wb-arch_usbf_wb" { } { { "usbf_wb.vhd" "" { Text "C:/Documents and Settings/xiehao/My Documents/my project/FPGA/usb/usbf_mem_arb/usbf_wb.vhd" 32 -1 0 } } } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 usbf_wb " "Info: Found entity 1: usbf_wb" { } { { "usbf_wb.vhd" "" { Text "C:/Documents and Settings/xiehao/My Documents/my project/FPGA/usb/usbf_mem_arb/usbf_wb.vhd" 5 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0} } { } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "usbf_mem_arb " "Info: Elaborating entity \"usbf_mem_arb\" for the top level hierarchy" { } { } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "sram_re VCC " "Warning: Pin \"sram_re\" stuck at VCC" { } { { "usbf_mem_arb.vhd" "" { Text "C:/Documents and Settings/xiehao/My Documents/my project/FPGA/usb/usbf_mem_arb/usbf_mem_arb.vhd" 14 -1 0 } } } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} } { } 0 0 "Output pins are stuck at VCC or GND" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "300 " "Info: Implemented 300 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "133 " "Info: Implemented 133 input pins" { } { } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "115 " "Info: Implemented 115 output pins" { } { } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "52 " "Info: Implemented 52 logic cells" { } { } 0 0 "Implemented %1!d! logic cells" 0 0} } { } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 2 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "134 " "Info: Allocated 134 megabytes of memory during processing" { } { } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Fri Jul 11 14:22:58 2008 " "Info: Processing ended: Fri Jul 11 14:22:58 2008" { } { } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
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