usbf_mem_arb.tan.qmsg

USB的 这次 我这只有两个可以上载 谁能告诉我怎么办

{ "Info" "ITDB_TH_RESULT" "wack_r wreq phy_clk -4.019 ns register " "Info: th for register \"wack_r\" (data pin = \"wreq\", clock pin = \"phy_clk\") is -4.019 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "phy_clk destination 2.049 ns + Longest register " "Info: + Longest clock path from clock \"phy_clk\" to destination register is 2.049 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.832 ns) 0.832 ns phy_clk 1 CLK PIN_L6 1 " "Info: 1: + IC(0.000 ns) + CELL(0.832 ns) = 0.832 ns; Loc. = PIN_L6; Fanout = 1; CLK Node = 'phy_clk'" {  } { { "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { phy_clk } "NODE_NAME" } } { "usbf_mem_arb.vhd" "" { Text "C:/Documents and Settings/xiehao/My Documents/my project/FPGA/usb/usbf_mem_arb/usbf_mem_arb.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.680 ns) + CELL(0.537 ns) 2.049 ns wack_r 2 REG LCFF_X1_Y24_N31 3 " "Info: 2: + IC(0.680 ns) + CELL(0.537 ns) = 2.049 ns; Loc. = LCFF_X1_Y24_N31; Fanout = 3; REG Node = 'wack_r'" {  } { { "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.217 ns" { phy_clk wack_r } "NODE_NAME" } } { "usbf_mem_arb.vhd" "" { Text "C:/Documents and Settings/xiehao/My Documents/my project/FPGA/usb/usbf_mem_arb/usbf_mem_arb.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.369 ns ( 66.81 % ) " "Info: Total cell delay = 1.369 ns ( 66.81 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.680 ns ( 33.19 % ) " "Info: Total interconnect delay = 0.680 ns ( 33.19 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.049 ns" { phy_clk wack_r } "NODE_NAME" } } { "d:/program files/altera/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus/bin/Technology_Viewer.qrui" "2.049 ns" { phy_clk phy_clk~combout wack_r } { 0.000ns 0.000ns 0.680ns } { 0.000ns 0.832ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.266 ns + " "Info: + Micro hold delay of destination is 0.266 ns" {  } { { "usbf_mem_arb.vhd" "" { Text "C:/Documents and Settings/xiehao/My Documents/my project/FPGA/usb/usbf_mem_arb/usbf_mem_arb.vhd" 34 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.334 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.334 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.870 ns) 0.870 ns wreq 1 PIN PIN_B4 3 " "Info: 1: + IC(0.000 ns) + CELL(0.870 ns) = 0.870 ns; Loc. = PIN_B4; Fanout = 3; PIN Node = 'wreq'" {  } { { "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { wreq } "NODE_NAME" } } { "usbf_mem_arb.vhd" "" { Text "C:/Documents and Settings/xiehao/My Documents/my project/FPGA/usb/usbf_mem_arb/usbf_mem_arb.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.230 ns) + CELL(0.150 ns) 6.250 ns wack_r~1 2 COMB LCCOMB_X1_Y24_N30 1 " "Info: 2: + IC(5.230 ns) + CELL(0.150 ns) = 6.250 ns; Loc. = LCCOMB_X1_Y24_N30; Fanout = 1; COMB Node = 'wack_r~1'" {  } { { "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "5.380 ns" { wreq wack_r~1 } "NODE_NAME" } } { "usbf_mem_arb.vhd" "" { Text "C:/Documents and Settings/xiehao/My Documents/my project/FPGA/usb/usbf_mem_arb/usbf_mem_arb.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 6.334 ns wack_r 3 REG LCFF_X1_Y24_N31 3 " "Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 6.334 ns; Loc. = LCFF_X1_Y24_N31; Fanout = 3; REG Node = 'wack_r'" {  } { { "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { wack_r~1 wack_r } "NODE_NAME" } } { "usbf_mem_arb.vhd" "" { Text "C:/Documents and Settings/xiehao/My Documents/my project/FPGA/usb/usbf_mem_arb/usbf_mem_arb.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.104 ns ( 17.43 % ) " "Info: Total cell delay = 1.104 ns ( 17.43 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.230 ns ( 82.57 % ) " "Info: Total interconnect delay = 5.230 ns ( 82.57 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "6.334 ns" { wreq wack_r~1 wack_r } "NODE_NAME" } } { "d:/program files/altera/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus/bin/Technology_Viewer.qrui" "6.334 ns" { wreq wreq~combout wack_r~1 wack_r } { 0.000ns 0.000ns 5.230ns 0.000ns } { 0.000ns 0.870ns 0.150ns 0.084ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.049 ns" { phy_clk wack_r } "NODE_NAME" } } { "d:/program files/altera/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus/bin/Technology_Viewer.qrui" "2.049 ns" { phy_clk phy_clk~combout wack_r } { 0.000ns 0.000ns 0.680ns } { 0.000ns 0.832ns 0.537ns } "" } } { "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "6.334 ns" { wreq wack_r~1 wack_r } "NODE_NAME" } } { "d:/program files/altera/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus/bin/Technology_Viewer.qrui" "6.334 ns" { wreq wreq~combout wack_r~1 wack_r } { 0.000ns 0.000ns 5.230ns 0.000ns } { 0.000ns 0.870ns 0.150ns 0.084ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "105 " "Info: Allocated 105 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Fri Jul 11 14:23:43 2008 " "Info: Processing ended: Fri Jul 11 14:23:43 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}