📄 usbf_mem_arb.tan.qmsg
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{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "phy_clk register register wack_r wack_r 450.05 MHz Internal " "Info: Clock \"phy_clk\" Internal fmax is restricted to 450.05 MHz between source register \"wack_r\" and destination register \"wack_r\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.222 ns " "Info: fmax restricted to clock pin edge rate 2.222 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.407 ns + Longest register register " "Info: + Longest register to register delay is 0.407 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns wack_r 1 REG LCFF_X1_Y24_N31 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y24_N31; Fanout = 3; REG Node = 'wack_r'" { } { { "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { wack_r } "NODE_NAME" } } { "usbf_mem_arb.vhd" "" { Text "C:/Documents and Settings/xiehao/My Documents/my project/FPGA/usb/usbf_mem_arb/usbf_mem_arb.vhd" 34 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.323 ns) 0.323 ns wack_r~1 2 COMB LCCOMB_X1_Y24_N30 1 " "Info: 2: + IC(0.000 ns) + CELL(0.323 ns) = 0.323 ns; Loc. = LCCOMB_X1_Y24_N30; Fanout = 1; COMB Node = 'wack_r~1'" { } { { "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.323 ns" { wack_r wack_r~1 } "NODE_NAME" } } { "usbf_mem_arb.vhd" "" { Text "C:/Documents and Settings/xiehao/My Documents/my project/FPGA/usb/usbf_mem_arb/usbf_mem_arb.vhd" 34 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 0.407 ns wack_r 3 REG LCFF_X1_Y24_N31 3 " "Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 0.407 ns; Loc. = LCFF_X1_Y24_N31; Fanout = 3; REG Node = 'wack_r'" { } { { "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { wack_r~1 wack_r } "NODE_NAME" } } { "usbf_mem_arb.vhd" "" { Text "C:/Documents and Settings/xiehao/My Documents/my project/FPGA/usb/usbf_mem_arb/usbf_mem_arb.vhd" 34 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.407 ns ( 100.00 % ) " "Info: Total cell delay = 0.407 ns ( 100.00 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} } { { "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.407 ns" { wack_r wack_r~1 wack_r } "NODE_NAME" } } { "d:/program files/altera/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus/bin/Technology_Viewer.qrui" "0.407 ns" { wack_r wack_r~1 wack_r } { 0.000ns 0.000ns 0.000ns } { 0.000ns 0.323ns 0.084ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "phy_clk destination 2.049 ns + Shortest register " "Info: + Shortest clock path from clock \"phy_clk\" to destination register is 2.049 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.832 ns) 0.832 ns phy_clk 1 CLK PIN_L6 1 " "Info: 1: + IC(0.000 ns) + CELL(0.832 ns) = 0.832 ns; Loc. = PIN_L6; Fanout = 1; CLK Node = 'phy_clk'" { } { { "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { phy_clk } "NODE_NAME" } } { "usbf_mem_arb.vhd" "" { Text "C:/Documents and Settings/xiehao/My Documents/my project/FPGA/usb/usbf_mem_arb/usbf_mem_arb.vhd" 10 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.680 ns) + CELL(0.537 ns) 2.049 ns wack_r 2 REG LCFF_X1_Y24_N31 3 " "Info: 2: + IC(0.680 ns) + CELL(0.537 ns) = 2.049 ns; Loc. = LCFF_X1_Y24_N31; Fanout = 3; REG Node = 'wack_r'" { } { { "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.217 ns" { phy_clk wack_r } "NODE_NAME" } } { "usbf_mem_arb.vhd" "" { Text "C:/Documents and Settings/xiehao/My Documents/my project/FPGA/usb/usbf_mem_arb/usbf_mem_arb.vhd" 34 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.369 ns ( 66.81 % ) " "Info: Total cell delay = 1.369 ns ( 66.81 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.680 ns ( 33.19 % ) " "Info: Total interconnect delay = 0.680 ns ( 33.19 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.049 ns" { phy_clk wack_r } "NODE_NAME" } } { "d:/program files/altera/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus/bin/Technology_Viewer.qrui" "2.049 ns" { phy_clk phy_clk~combout wack_r } { 0.000ns 0.000ns 0.680ns } { 0.000ns 0.832ns 0.537ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "phy_clk source 2.049 ns - Longest register " "Info: - Longest clock path from clock \"phy_clk\" to source register is 2.049 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.832 ns) 0.832 ns phy_clk 1 CLK PIN_L6 1 " "Info: 1: + IC(0.000 ns) + CELL(0.832 ns) = 0.832 ns; Loc. = PIN_L6; Fanout = 1; CLK Node = 'phy_clk'" { } { { "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { phy_clk } "NODE_NAME" } } { "usbf_mem_arb.vhd" "" { Text "C:/Documents and Settings/xiehao/My Documents/my project/FPGA/usb/usbf_mem_arb/usbf_mem_arb.vhd" 10 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.680 ns) + CELL(0.537 ns) 2.049 ns wack_r 2 REG LCFF_X1_Y24_N31 3 " "Info: 2: + IC(0.680 ns) + CELL(0.537 ns) = 2.049 ns; Loc. = LCFF_X1_Y24_N31; Fanout = 3; REG Node = 'wack_r'" { } { { "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.217 ns" { phy_clk wack_r } "NODE_NAME" } } { "usbf_mem_arb.vhd" "" { Text "C:/Documents and Settings/xiehao/My Documents/my project/FPGA/usb/usbf_mem_arb/usbf_mem_arb.vhd" 34 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.369 ns ( 66.81 % ) " "Info: Total cell delay = 1.369 ns ( 66.81 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.680 ns ( 33.19 % ) " "Info: Total interconnect delay = 0.680 ns ( 33.19 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.049 ns" { phy_clk wack_r } "NODE_NAME" } } { "d:/program files/altera/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus/bin/Technology_Viewer.qrui" "2.049 ns" { phy_clk phy_clk~combout wack_r } { 0.000ns 0.000ns 0.680ns } { 0.000ns 0.832ns 0.537ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.049 ns" { phy_clk wack_r } "NODE_NAME" } } { "d:/program files/altera/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus/bin/Technology_Viewer.qrui" "2.049 ns" { phy_clk phy_clk~combout wack_r } { 0.000ns 0.000ns 0.680ns } { 0.000ns 0.832ns 0.537ns } "" } } { "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.049 ns" { phy_clk wack_r } "NODE_NAME" } } { "d:/program files/altera/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus/bin/Technology_Viewer.qrui" "2.049 ns" { phy_clk phy_clk~combout wack_r } { 0.000ns 0.000ns 0.680ns } { 0.000ns 0.832ns 0.537ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" { } { { "usbf_mem_arb.vhd" "" { Text "C:/Documents and Settings/xiehao/My Documents/my project/FPGA/usb/usbf_mem_arb/usbf_mem_arb.vhd" 34 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" { } { { "usbf_mem_arb.vhd" "" { Text "C:/Documents and Settings/xiehao/My Documents/my project/FPGA/usb/usbf_mem_arb/usbf_mem_arb.vhd" 34 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} } { { "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.407 ns" { wack_r wack_r~1 wack_r } "NODE_NAME" } } { "d:/program files/altera/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus/bin/Technology_Viewer.qrui" "0.407 ns" { wack_r wack_r~1 wack_r } { 0.000ns 0.000ns 0.000ns } { 0.000ns 0.323ns 0.084ns } "" } } { "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.049 ns" { phy_clk wack_r } "NODE_NAME" } } { "d:/program files/altera/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus/bin/Technology_Viewer.qrui" "2.049 ns" { phy_clk phy_clk~combout wack_r } { 0.000ns 0.000ns 0.680ns } { 0.000ns 0.832ns 0.537ns } "" } } { "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.049 ns" { phy_clk wack_r } "NODE_NAME" } } { "d:/program files/altera/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus/bin/Technology_Viewer.qrui" "2.049 ns" { phy_clk phy_clk~combout wack_r } { 0.000ns 0.000ns 0.680ns } { 0.000ns 0.832ns 0.537ns } "" } } } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0} } { { "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { wack_r } "NODE_NAME" } } { "d:/program files/altera/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus/bin/Technology_Viewer.qrui" "" { wack_r } { } { } "" } } { "usbf_mem_arb.vhd" "" { Text "C:/Documents and Settings/xiehao/My Documents/my project/FPGA/usb/usbf_mem_arb/usbf_mem_arb.vhd" 34 -1 0 } } } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_TSU_RESULT" "wack_r mreq phy_clk 4.323 ns register " "Info: tsu for register \"wack_r\" (data pin = \"mreq\", clock pin = \"phy_clk\") is 4.323 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.408 ns + Longest pin register " "Info: + Longest pin to register delay is 6.408 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.842 ns) 0.842 ns mreq 1 PIN PIN_G4 5 " "Info: 1: + IC(0.000 ns) + CELL(0.842 ns) = 0.842 ns; Loc. = PIN_G4; Fanout = 5; PIN Node = 'mreq'" { } { { "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { mreq } "NODE_NAME" } } { "usbf_mem_arb.vhd" "" { Text "C:/Documents and Settings/xiehao/My Documents/my project/FPGA/usb/usbf_mem_arb/usbf_mem_arb.vhd" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.111 ns) + CELL(0.371 ns) 6.324 ns wack_r~1 2 COMB LCCOMB_X1_Y24_N30 1 " "Info: 2: + IC(5.111 ns) + CELL(0.371 ns) = 6.324 ns; Loc. = LCCOMB_X1_Y24_N30; Fanout = 1; COMB Node = 'wack_r~1'" { } { { "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "5.482 ns" { mreq wack_r~1 } "NODE_NAME" } } { "usbf_mem_arb.vhd" "" { Text "C:/Documents and Settings/xiehao/My Documents/my project/FPGA/usb/usbf_mem_arb/usbf_mem_arb.vhd" 34 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 6.408 ns wack_r 3 REG LCFF_X1_Y24_N31 3 " "Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 6.408 ns; Loc. = LCFF_X1_Y24_N31; Fanout = 3; REG Node = 'wack_r'" { } { { "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { wack_r~1 wack_r } "NODE_NAME" } } { "usbf_mem_arb.vhd" "" { Text "C:/Documents and Settings/xiehao/My Documents/my project/FPGA/usb/usbf_mem_arb/usbf_mem_arb.vhd" 34 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.297 ns ( 20.24 % ) " "Info: Total cell delay = 1.297 ns ( 20.24 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.111 ns ( 79.76 % ) " "Info: Total interconnect delay = 5.111 ns ( 79.76 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "6.408 ns" { mreq wack_r~1 wack_r } "NODE_NAME" } } { "d:/program files/altera/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus/bin/Technology_Viewer.qrui" "6.408 ns" { mreq mreq~combout wack_r~1 wack_r } { 0.000ns 0.000ns 5.111ns 0.000ns } { 0.000ns 0.842ns 0.371ns 0.084ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" { } { { "usbf_mem_arb.vhd" "" { Text "C:/Documents and Settings/xiehao/My Documents/my project/FPGA/usb/usbf_mem_arb/usbf_mem_arb.vhd" 34 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "phy_clk destination 2.049 ns - Shortest register " "Info: - Shortest clock path from clock \"phy_clk\" to destination register is 2.049 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.832 ns) 0.832 ns phy_clk 1 CLK PIN_L6 1 " "Info: 1: + IC(0.000 ns) + CELL(0.832 ns) = 0.832 ns; Loc. = PIN_L6; Fanout = 1; CLK Node = 'phy_clk'" { } { { "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { phy_clk } "NODE_NAME" } } { "usbf_mem_arb.vhd" "" { Text "C:/Documents and Settings/xiehao/My Documents/my project/FPGA/usb/usbf_mem_arb/usbf_mem_arb.vhd" 10 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.680 ns) + CELL(0.537 ns) 2.049 ns wack_r 2 REG LCFF_X1_Y24_N31 3 " "Info: 2: + IC(0.680 ns) + CELL(0.537 ns) = 2.049 ns; Loc. = LCFF_X1_Y24_N31; Fanout = 3; REG Node = 'wack_r'" { } { { "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.217 ns" { phy_clk wack_r } "NODE_NAME" } } { "usbf_mem_arb.vhd" "" { Text "C:/Documents and Settings/xiehao/My Documents/my project/FPGA/usb/usbf_mem_arb/usbf_mem_arb.vhd" 34 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.369 ns ( 66.81 % ) " "Info: Total cell delay = 1.369 ns ( 66.81 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.680 ns ( 33.19 % ) " "Info: Total interconnect delay = 0.680 ns ( 33.19 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.049 ns" { phy_clk wack_r } "NODE_NAME" } } { "d:/program files/altera/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus/bin/Technology_Viewer.qrui" "2.049 ns" { phy_clk phy_clk~combout wack_r } { 0.000ns 0.000ns 0.680ns } { 0.000ns 0.832ns 0.537ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "6.408 ns" { mreq wack_r~1 wack_r } "NODE_NAME" } } { "d:/program files/altera/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus/bin/Technology_Viewer.qrui" "6.408 ns" { mreq mreq~combout wack_r~1 wack_r } { 0.000ns 0.000ns 5.111ns 0.000ns } { 0.000ns 0.842ns 0.371ns 0.084ns } "" } } { "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.049 ns" { phy_clk wack_r } "NODE_NAME" } } { "d:/program files/altera/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus/bin/Technology_Viewer.qrui" "2.049 ns" { phy_clk phy_clk~combout wack_r } { 0.000ns 0.000ns 0.680ns } { 0.000ns 0.832ns 0.537ns } "" } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "phy_clk sram_dout\[4\] wack_r 12.748 ns register " "Info: tco from clock \"phy_clk\" to destination pin \"sram_dout\[4\]\" through register \"wack_r\" is 12.748 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "phy_clk source 2.049 ns + Longest register " "Info: + Longest clock path from clock \"phy_clk\" to source register is 2.049 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.832 ns) 0.832 ns phy_clk 1 CLK PIN_L6 1 " "Info: 1: + IC(0.000 ns) + CELL(0.832 ns) = 0.832 ns; Loc. = PIN_L6; Fanout = 1; CLK Node = 'phy_clk'" { } { { "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { phy_clk } "NODE_NAME" } } { "usbf_mem_arb.vhd" "" { Text "C:/Documents and Settings/xiehao/My Documents/my project/FPGA/usb/usbf_mem_arb/usbf_mem_arb.vhd" 10 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.680 ns) + CELL(0.537 ns) 2.049 ns wack_r 2 REG LCFF_X1_Y24_N31 3 " "Info: 2: + IC(0.680 ns) + CELL(0.537 ns) = 2.049 ns; Loc. = LCFF_X1_Y24_N31; Fanout = 3; REG Node = 'wack_r'" { } { { "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.217 ns" { phy_clk wack_r } "NODE_NAME" } } { "usbf_mem_arb.vhd" "" { Text "C:/Documents and Settings/xiehao/My Documents/my project/FPGA/usb/usbf_mem_arb/usbf_mem_arb.vhd" 34 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.369 ns ( 66.81 % ) " "Info: Total cell delay = 1.369 ns ( 66.81 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.680 ns ( 33.19 % ) " "Info: Total interconnect delay = 0.680 ns ( 33.19 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.049 ns" { phy_clk wack_r } "NODE_NAME" } } { "d:/program files/altera/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus/bin/Technology_Viewer.qrui" "2.049 ns" { phy_clk phy_clk~combout wack_r } { 0.000ns 0.000ns 0.680ns } { 0.000ns 0.832ns 0.537ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" { } { { "usbf_mem_arb.vhd" "" { Text "C:/Documents and Settings/xiehao/My Documents/my project/FPGA/usb/usbf_mem_arb/usbf_mem_arb.vhd" 34 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.449 ns + Longest register pin " "Info: + Longest register to pin delay is 10.449 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns wack_r 1 REG LCFF_X1_Y24_N31 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y24_N31; Fanout = 3; REG Node = 'wack_r'" { } { { "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { wack_r } "NODE_NAME" } } { "usbf_mem_arb.vhd" "" { Text "C:/Documents and Settings/xiehao/My Documents/my project/FPGA/usb/usbf_mem_arb/usbf_mem_arb.vhd" 34 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.305 ns) + CELL(0.150 ns) 0.455 ns wsel~19 2 COMB LCCOMB_X1_Y24_N10 47 " "Info: 2: + IC(0.305 ns) + CELL(0.150 ns) = 0.455 ns; Loc. = LCCOMB_X1_Y24_N10; Fanout = 47; COMB Node = 'wsel~19'" { } { { "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.455 ns" { wack_r wsel~19 } "NODE_NAME" } } { "usbf_mem_arb.vhd" "" { Text "C:/Documents and Settings/xiehao/My Documents/my project/FPGA/usb/usbf_mem_arb/usbf_mem_arb.vhd" 32 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.816 ns) + CELL(0.420 ns) 4.691 ns sram_dout~2052 3 COMB LCCOMB_X61_Y7_N24 1 " "Info: 3: + IC(3.816 ns) + CELL(0.420 ns) = 4.691 ns; Loc. = LCCOMB_X61_Y7_N24; Fanout = 1; COMB Node = 'sram_dout~2052'" { } { { "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "4.236 ns" { wsel~19 sram_dout~2052 } "NODE_NAME" } } { "usbf_mem_arb.vhd" "" { Text "C:/Documents and Settings/xiehao/My Documents/my project/FPGA/usb/usbf_mem_arb/usbf_mem_arb.vhd" 13 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.126 ns) + CELL(2.632 ns) 10.449 ns sram_dout\[4\] 4 PIN PIN_Y3 0 " "Info: 4: + IC(3.126 ns) + CELL(2.632 ns) = 10.449 ns; Loc. = PIN_Y3; Fanout = 0; PIN Node = 'sram_dout\[4\]'" { } { { "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "5.758 ns" { sram_dout~2052 sram_dout[4] } "NODE_NAME" } } { "usbf_mem_arb.vhd" "" { Text "C:/Documents and Settings/xiehao/My Documents/my project/FPGA/usb/usbf_mem_arb/usbf_mem_arb.vhd" 13 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.202 ns ( 30.64 % ) " "Info: Total cell delay = 3.202 ns ( 30.64 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.247 ns ( 69.36 % ) " "Info: Total interconnect delay = 7.247 ns ( 69.36 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "10.449 ns" { wack_r wsel~19 sram_dout~2052 sram_dout[4] } "NODE_NAME" } } { "d:/program files/altera/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus/bin/Technology_Viewer.qrui" "10.449 ns" { wack_r wsel~19 sram_dout~2052 sram_dout[4] } { 0.000ns 0.305ns 3.816ns 3.126ns } { 0.000ns 0.150ns 0.420ns 2.632ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} } { { "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.049 ns" { phy_clk wack_r } "NODE_NAME" } } { "d:/program files/altera/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus/bin/Technology_Viewer.qrui" "2.049 ns" { phy_clk phy_clk~combout wack_r } { 0.000ns 0.000ns 0.680ns } { 0.000ns 0.832ns 0.537ns } "" } } { "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "10.449 ns" { wack_r wsel~19 sram_dout~2052 sram_dout[4] } "NODE_NAME" } } { "d:/program files/altera/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus/bin/Technology_Viewer.qrui" "10.449 ns" { wack_r wsel~19 sram_dout~2052 sram_dout[4] } { 0.000ns 0.305ns 3.816ns 3.126ns } { 0.000ns 0.150ns 0.420ns 2.632ns } "" } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "wreq sram_dout\[4\] 16.599 ns Longest " "Info: Longest tpd from source pin \"wreq\" to destination pin \"sram_dout\[4\]\" is 16.599 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.870 ns) 0.870 ns wreq 1 PIN PIN_B4 3 " "Info: 1: + IC(0.000 ns) + CELL(0.870 ns) = 0.870 ns; Loc. = PIN_B4; Fanout = 3; PIN Node = 'wreq'" { } { { "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { wreq } "NODE_NAME" } } { "usbf_mem_arb.vhd" "" { Text "C:/Documents and Settings/xiehao/My Documents/my project/FPGA/usb/usbf_mem_arb/usbf_mem_arb.vhd" 26 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.460 ns) + CELL(0.275 ns) 6.605 ns wsel~19 2 COMB LCCOMB_X1_Y24_N10 47 " "Info: 2: + IC(5.460 ns) + CELL(0.275 ns) = 6.605 ns; Loc. = LCCOMB_X1_Y24_N10; Fanout = 47; COMB Node = 'wsel~19'" { } { { "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "5.735 ns" { wreq wsel~19 } "NODE_NAME" } } { "usbf_mem_arb.vhd" "" { Text "C:/Documents and Settings/xiehao/My Documents/my project/FPGA/usb/usbf_mem_arb/usbf_mem_arb.vhd" 32 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.816 ns) + CELL(0.420 ns) 10.841 ns sram_dout~2052 3 COMB LCCOMB_X61_Y7_N24 1 " "Info: 3: + IC(3.816 ns) + CELL(0.420 ns) = 10.841 ns; Loc. = LCCOMB_X61_Y7_N24; Fanout = 1; COMB Node = 'sram_dout~2052'" { } { { "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "4.236 ns" { wsel~19 sram_dout~2052 } "NODE_NAME" } } { "usbf_mem_arb.vhd" "" { Text "C:/Documents and Settings/xiehao/My Documents/my project/FPGA/usb/usbf_mem_arb/usbf_mem_arb.vhd" 13 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.126 ns) + CELL(2.632 ns) 16.599 ns sram_dout\[4\] 4 PIN PIN_Y3 0 " "Info: 4: + IC(3.126 ns) + CELL(2.632 ns) = 16.599 ns; Loc. = PIN_Y3; Fanout = 0; PIN Node = 'sram_dout\[4\]'" { } { { "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "5.758 ns" { sram_dout~2052 sram_dout[4] } "NODE_NAME" } } { "usbf_mem_arb.vhd" "" { Text "C:/Documents and Settings/xiehao/My Documents/my project/FPGA/usb/usbf_mem_arb/usbf_mem_arb.vhd" 13 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.197 ns ( 25.28 % ) " "Info: Total cell delay = 4.197 ns ( 25.28 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "12.402 ns ( 74.72 % ) " "Info: Total interconnect delay = 12.402 ns ( 74.72 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus/bin/TimingClosureFloorplan.fld" "" "16.599 ns" { wreq wsel~19 sram_dout~2052 sram_dout[4] } "NODE_NAME" } } { "d:/program files/altera/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus/bin/Technology_Viewer.qrui" "16.599 ns" { wreq wreq~combout wsel~19 sram_dout~2052 sram_dout[4] } { 0.000ns 0.000ns 5.460ns 3.816ns 3.126ns } { 0.000ns 0.870ns 0.275ns 0.420ns 2.632ns } "" } } } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
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