usbf_mem_arb.tan.qmsg

USB的 这次 我这只有两个可以上载 谁能告诉我怎么办

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.1 Build 201 11/27/2006 SJ Web Edition " "Info: Version 6.1 Build 201 11/27/2006 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Jul 11 14:23:42 2008 " "Info: Processing started: Fri Jul 11 14:23:42 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off usbf_mem_arb -c usbf_mem_arb --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off usbf_mem_arb -c usbf_mem_arb --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "phy_clk " "Info: Assuming node \"phy_clk\" is an undefined clock" {  } { { "usbf_mem_arb.vhd" "" { Text "C:/Documents and Settings/xiehao/My Documents/my project/FPGA/usb/usbf_mem_arb/usbf_mem_arb.vhd" 10 -1 0 } } { "d:/program files/altera/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus/bin/Assignment Editor.qase" 1 { { 0 "phy_clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}