usbf_mem_arb.tan.rpt

USB的 这次 我这只有两个可以上载 谁能告诉我怎么办

; N/A                                     ; None                                                ; 9.107 ns        ; wdin[26]     ; sram_dout[26] ;
; N/A                                     ; None                                                ; 9.022 ns        ; sram_din[24] ; mdout[24]     ;
; N/A                                     ; None                                                ; 8.966 ns        ; wdin[28]     ; sram_dout[28] ;
; N/A                                     ; None                                                ; 8.925 ns        ; sram_din[10] ; wdout[10]     ;
; N/A                                     ; None                                                ; 8.924 ns        ; sram_din[22] ; wdout[22]     ;
; N/A                                     ; None                                                ; 8.924 ns        ; sram_din[22] ; mdout[22]     ;
; N/A                                     ; None                                                ; 8.919 ns        ; sram_din[18] ; wdout[18]     ;
; N/A                                     ; None                                                ; 8.919 ns        ; sram_din[18] ; mdout[18]     ;
; N/A                                     ; None                                                ; 8.913 ns        ; sram_din[4]  ; mdout[4]      ;
; N/A                                     ; None                                                ; 8.905 ns        ; sram_din[4]  ; wdout[4]      ;
; N/A                                     ; None                                                ; 8.894 ns        ; sram_din[10] ; mdout[10]     ;
; N/A                                     ; None                                                ; 8.871 ns        ; sram_din[14] ; mdout[14]     ;
; N/A                                     ; None                                                ; 8.866 ns        ; sram_din[14] ; wdout[14]     ;
; N/A                                     ; None                                                ; 8.857 ns        ; madr[11]     ; sram_adr[11]  ;
; N/A                                     ; None                                                ; 8.849 ns        ; sram_din[15] ; wdout[15]     ;
; N/A                                     ; None                                                ; 8.849 ns        ; sram_din[15] ; mdout[15]     ;
; N/A                                     ; None                                                ; 8.837 ns        ; sram_din[6]  ; mdout[6]      ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;                 ;              ;               ;
+-----------------------------------------+-----------------------------------------------------+-----------------+--------------+---------------+


+--------------------------------------------------------------------+
; th                                                                 ;
+---------------+-------------+-----------+------+--------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To     ; To Clock ;
+---------------+-------------+-----------+------+--------+----------+
; N/A           ; None        ; -4.019 ns ; wreq ; wack_r ; phy_clk  ;
; N/A           ; None        ; -4.093 ns ; mreq ; wack_r ; phy_clk  ;
+---------------+-------------+-----------+------+--------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 6.1 Build 201 11/27/2006 SJ Web Edition
    Info: Processing started: Fri Jul 11 14:23:42 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off usbf_mem_arb -c usbf_mem_arb --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "phy_clk" is an undefined clock
Info: Clock "phy_clk" Internal fmax is restricted to 450.05 MHz between source register "wack_r" and destination register "wack_r"
    Info: fmax restricted to clock pin edge rate 2.222 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 0.407 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y24_N31; Fanout = 3; REG Node = 'wack_r'
            Info: 2: + IC(0.000 ns) + CELL(0.323 ns) = 0.323 ns; Loc. = LCCOMB_X1_Y24_N30; Fanout = 1; COMB Node = 'wack_r~1'
            Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 0.407 ns; Loc. = LCFF_X1_Y24_N31; Fanout = 3; REG Node = 'wack_r'
            Info: Total cell delay = 0.407 ns ( 100.00 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "phy_clk" to destination register is 2.049 ns
                Info: 1: + IC(0.000 ns) + CELL(0.832 ns) = 0.832 ns; Loc. = PIN_L6; Fanout = 1; CLK Node = 'phy_clk'
                Info: 2: + IC(0.680 ns) + CELL(0.537 ns) = 2.049 ns; Loc. = LCFF_X1_Y24_N31; Fanout = 3; REG Node = 'wack_r'
                Info: Total cell delay = 1.369 ns ( 66.81 % )
                Info: Total interconnect delay = 0.680 ns ( 33.19 % )
            Info: - Longest clock path from clock "phy_clk" to source register is 2.049 ns
                Info: 1: + IC(0.000 ns) + CELL(0.832 ns) = 0.832 ns; Loc. = PIN_L6; Fanout = 1; CLK Node = 'phy_clk'
                Info: 2: + IC(0.680 ns) + CELL(0.537 ns) = 2.049 ns; Loc. = LCFF_X1_Y24_N31; Fanout = 3; REG Node = 'wack_r'
                Info: Total cell delay = 1.369 ns ( 66.81 % )
                Info: Total interconnect delay = 0.680 ns ( 33.19 % )
        Info: + Micro clock to output delay of source is 0.250 ns
        Info: + Micro setup delay of destination is -0.036 ns
Info: tsu for register "wack_r" (data pin = "mreq", clock pin = "phy_clk") is 4.323 ns
    Info: + Longest pin to register delay is 6.408 ns
        Info: 1: + IC(0.000 ns) + CELL(0.842 ns) = 0.842 ns; Loc. = PIN_G4; Fanout = 5; PIN Node = 'mreq'
        Info: 2: + IC(5.111 ns) + CELL(0.371 ns) = 6.324 ns; Loc. = LCCOMB_X1_Y24_N30; Fanout = 1; COMB Node = 'wack_r~1'
        Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 6.408 ns; Loc. = LCFF_X1_Y24_N31; Fanout = 3; REG Node = 'wack_r'
        Info: Total cell delay = 1.297 ns ( 20.24 % )
        Info: Total interconnect delay = 5.111 ns ( 79.76 % )
    Info: + Micro setup delay of destination is -0.036 ns
    Info: - Shortest clock path from clock "phy_clk" to destination register is 2.049 ns
        Info: 1: + IC(0.000 ns) + CELL(0.832 ns) = 0.832 ns; Loc. = PIN_L6; Fanout = 1; CLK Node = 'phy_clk'
        Info: 2: + IC(0.680 ns) + CELL(0.537 ns) = 2.049 ns; Loc. = LCFF_X1_Y24_N31; Fanout = 3; REG Node = 'wack_r'
        Info: Total cell delay = 1.369 ns ( 66.81 % )
        Info: Total interconnect delay = 0.680 ns ( 33.19 % )
Info: tco from clock "phy_clk" to destination pin "sram_dout[4]" through register "wack_r" is 12.748 ns
    Info: + Longest clock path from clock "phy_clk" to source register is 2.049 ns
        Info: 1: + IC(0.000 ns) + CELL(0.832 ns) = 0.832 ns; Loc. = PIN_L6; Fanout = 1; CLK Node = 'phy_clk'
        Info: 2: + IC(0.680 ns) + CELL(0.537 ns) = 2.049 ns; Loc. = LCFF_X1_Y24_N31; Fanout = 3; REG Node = 'wack_r'
        Info: Total cell delay = 1.369 ns ( 66.81 % )
        Info: Total interconnect delay = 0.680 ns ( 33.19 % )
    Info: + Micro clock to output delay of source is 0.250 ns
    Info: + Longest register to pin delay is 10.449 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y24_N31; Fanout = 3; REG Node = 'wack_r'
        Info: 2: + IC(0.305 ns) + CELL(0.150 ns) = 0.455 ns; Loc. = LCCOMB_X1_Y24_N10; Fanout = 47; COMB Node = 'wsel~19'
        Info: 3: + IC(3.816 ns) + CELL(0.420 ns) = 4.691 ns; Loc. = LCCOMB_X61_Y7_N24; Fanout = 1; COMB Node = 'sram_dout~2052'
        Info: 4: + IC(3.126 ns) + CELL(2.632 ns) = 10.449 ns; Loc. = PIN_Y3; Fanout = 0; PIN Node = 'sram_dout[4]'
        Info: Total cell delay = 3.202 ns ( 30.64 % )
        Info: Total interconnect delay = 7.247 ns ( 69.36 % )
Info: Longest tpd from source pin "wreq" to destination pin "sram_dout[4]" is 16.599 ns
    Info: 1: + IC(0.000 ns) + CELL(0.870 ns) = 0.870 ns; Loc. = PIN_B4; Fanout = 3; PIN Node = 'wreq'
    Info: 2: + IC(5.460 ns) + CELL(0.275 ns) = 6.605 ns; Loc. = LCCOMB_X1_Y24_N10; Fanout = 47; COMB Node = 'wsel~19'
    Info: 3: + IC(3.816 ns) + CELL(0.420 ns) = 10.841 ns; Loc. = LCCOMB_X61_Y7_N24; Fanout = 1; COMB Node = 'sram_dout~2052'
    Info: 4: + IC(3.126 ns) + CELL(2.632 ns) = 16.599 ns; Loc. = PIN_Y3; Fanout = 0; PIN Node = 'sram_dout[4]'
    Info: Total cell delay = 4.197 ns ( 25.28 % )
    Info: Total interconnect delay = 12.402 ns ( 74.72 % )
Info: th for register "wack_r" (data pin = "wreq", clock pin = "phy_clk") is -4.019 ns
    Info: + Longest clock path from clock "phy_clk" to destination register is 2.049 ns
        Info: 1: + IC(0.000 ns) + CELL(0.832 ns) = 0.832 ns; Loc. = PIN_L6; Fanout = 1; CLK Node = 'phy_clk'
        Info: 2: + IC(0.680 ns) + CELL(0.537 ns) = 2.049 ns; Loc. = LCFF_X1_Y24_N31; Fanout = 3; REG Node = 'wack_r'
        Info: Total cell delay = 1.369 ns ( 66.81 % )
        Info: Total interconnect delay = 0.680 ns ( 33.19 % )
    Info: + Micro hold delay of destination is 0.266 ns
    Info: - Shortest pin to register delay is 6.334 ns
        Info: 1: + IC(0.000 ns) + CELL(0.870 ns) = 0.870 ns; Loc. = PIN_B4; Fanout = 3; PIN Node = 'wreq'
        Info: 2: + IC(5.230 ns) + CELL(0.150 ns) = 6.250 ns; Loc. = LCCOMB_X1_Y24_N30; Fanout = 1; COMB Node = 'wack_r~1'
        Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 6.334 ns; Loc. = LCFF_X1_Y24_N31; Fanout = 3; REG Node = 'wack_r'
        Info: Total cell delay = 1.104 ns ( 17.43 % )
        Info: Total interconnect delay = 5.230 ns ( 82.57 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 105 megabytes of memory during processing
    Info: Processing ended: Fri Jul 11 14:23:43 2008
    Info: Elapsed time: 00:00:01