usbf_mem_arb.map.rpt

USB的 这次 我这只有两个可以上载 谁能告诉我怎么办

; Ignore Maximum Fan-Out Assignments                                 ; Off                ; Off                ;
; Retiming Meta-Stability Register Sequence Length                   ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                       ; Normal compilation ; Normal compilation ;
; HDL message level                                                  ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages                    ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report           ; 100                ; 100                ;
; Use smart compilation                                              ; Off                ; Off                ;
+--------------------------------------------------------------------+--------------------+--------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                                 ;
+----------------------------------+-----------------+-----------------+-------------------------------------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type       ; File Name with Absolute Path                                                                    ;
+----------------------------------+-----------------+-----------------+-------------------------------------------------------------------------------------------------+
; usbf_mem_arb.vhd                 ; yes             ; User VHDL File  ; C:/Documents and Settings/xiehao/My Documents/my project/FPGA/usb/usbf_mem_arb/usbf_mem_arb.vhd ;
+----------------------------------+-----------------+-----------------+-------------------------------------------------------------------------------------------------+


+-------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary           ;
+---------------------------------------------+---------+
; Resource                                    ; Usage   ;
+---------------------------------------------+---------+
; Estimated Total logic elements              ; 52      ;
;                                             ;         ;
; Total combinational functions               ; 52      ;
; Logic element usage by number of LUT inputs ;         ;
;     -- 4 input functions                    ; 1       ;
;     -- 3 input functions                    ; 49      ;
;     -- <=2 input functions                  ; 2       ;
;                                             ;         ;
; Logic elements by mode                      ;         ;
;     -- normal mode                          ; 52      ;
;     -- arithmetic mode                      ; 0       ;
;                                             ;         ;
; Total registers                             ; 1       ;
;     -- Dedicated logic registers            ; 1       ;
;     -- I/O registers                        ; 0       ;
;                                             ;         ;
; I/O pins                                    ; 0       ;
; Maximum fan-out node                        ; wsel~19 ;
; Maximum fan-out                             ; 47      ;
; Total fan-out                               ; 271     ;
; Average fan-out                             ; 0.90    ;
+---------------------------------------------+---------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                          ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+
; |usbf_mem_arb              ; 52 (52)           ; 1 (1)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |usbf_mem_arb       ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 1     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 1     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: Top-level Entity: |usbf_mem_arb ;
+----------------+-------+-----------------------------------------------------+
; Parameter Name ; Value ; Type                                                ;
+----------------+-------+-----------------------------------------------------+
; ssram_hadr     ; 14    ; Signed Integer                                      ;
+----------------+-------+-----------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.1 Build 201 11/27/2006 SJ Web Edition
    Info: Processing started: Fri Jul 11 14:22:56 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off usbf_mem_arb -c usbf_mem_arb
Info: Found 2 design units, including 1 entities, in source file usbf_mem_arb.vhd
    Info: Found design unit 1: usbf_mem_arb-arch_of_mem_arb
    Info: Found entity 1: usbf_mem_arb
Info: Found 2 design units, including 1 entities, in source file usbf_wb.vhd
    Info: Found design unit 1: usbf_wb-arch_usbf_wb
    Info: Found entity 1: usbf_wb
Info: Elaborating entity "usbf_mem_arb" for the top level hierarchy
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "sram_re" stuck at VCC
Info: Implemented 300 device resources after synthesis - the final resource count might be different
    Info: Implemented 133 input pins
    Info: Implemented 115 output pins
    Info: Implemented 52 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings
    Info: Allocated 134 megabytes of memory during processing
    Info: Processing ended: Fri Jul 11 14:22:58 2008
    Info: Elapsed time: 00:00:02