usbf_mem_arb.vhd

USB的 这次 我这只有两个可以上载 谁能告诉我怎么办

-- file usbf_mem_arb
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity usbf_mem_arb is
 generic(ssram_hadr	: integer :=14);
 port
 (
	phy_clk,wclk,rst	:in std_logic;
	sram_adr	:buffer std_logic_vector(ssram_hadr downto 0);
	sram_din	:in std_logic_vector(31 downto 0);
	sram_dout	:buffer std_logic_vector(31 downto 0);
	sram_re,sram_we: out std_logic;
	madr		:in std_logic_vector(ssram_hadr downto 0);
	mdout		:out std_logic_vector(31 downto 0);
	mdin		:in std_logic_vector(31 downto 0);
	mwe			:in std_logic;
	mreq		:in std_logic;
	mack		:buffer std_logic;
	--内部接口操作	
	wadr		:in std_logic_vector(ssram_hadr downto 0);
	wdout		:out std_logic_vector(31 downto 0);
	wdin		:in std_logic_vector(31 downto 0);
	wwe			:in std_logic;
	wreq		:in std_logic;
	wack		:buffer std_logic
 );
end entity;

architecture arch_of_mem_arb of usbf_mem_arb is
signal wsel:std_logic;
signal mcyc:std_logic;
signal wack_r:std_logic;
begin
wsel<=(wreq or wack)and not(mreq);
process(wsel,wdin,mdin)
	begin
	 if wsel='1' then
		sram_dout<=wdin;
	 else
		sram_dout<=mdin;
	 end if;
end process;

--sram 地址线输出
process(wsel,wadr,madr)
 	begin
		if wsel='1' then 
			sram_adr<=wadr;
		else
			sram_adr<=madr;
		end if;
end process;
process(wsel,wwe,wreq,mwe,mcyc)
 	begin
		if wsel='1' then
			sram_we<=wreq and wwe;
		else
		 	sram_we<=mwe and mcyc;
		end if;
end process;

sram_re<='1';
mdout<=sram_din;
mack<=mreq;
mcyc<=mack;
wdout<=sram_din;
wack<=wack_r and not(mreq);


process(rst,phy_clk)
begin
 if rst='0' then
 	wack_r<='0';
 elsif(phy_clk'event and phy_clk='1') then
	wack_r<=wreq and not(mreq) and not(wack);
 end if;
end process;
end architecture;