📄 start167.lst
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646 ; 8*KB (gives RGSZ1 = 1)
647 ; 16*KB (gives RGSZ1 = 2)
648 ; 32*KB (gives RGSZ1 = 3)
A166 MACRO ASSEMBLER START167 10/01/2008 12:25:59 PAGE 11
649 ; 64*KB (gives RGSZ1 = 4)
650 ; 128*KB (gives RGSZ1 = 5)
651 ; 256*KB (gives RGSZ1 = 6)
652 ; 512*KB (gives RGSZ1 = 7)
653 ; 1024*KB or 1*MB (gives RGSZ1 = 8)
654 ; 2048*KB or 2*MB (gives RGSZ1 = 9)
655 ; 4096*KB or 4*MB (gives RGSZ1 = 10)
656 ; 8192*KB or 8*MB (gives RGSZ1 = 11)
657 ; (RGSZ1 = 12 .. 15 reserved)
658 ;</h>
659 ;
660 ; <h>Definitions for Function Configuration Register FCONCS1
661 ; ==========================================================
662 ;
663 ; <q> ENCS1: Enable Chip Select (FCONCS1.0)
0001 664 _ENCS1 EQU 1 ; 0 = Chip Select 0 disabled
665 ; 1 = Chip Select 0 enabled
666 ;
667 ; <q> RDYEN1: Ready Enable (FCONCS1.1)
0000 668 _RDYEN1 EQU 0 ; 0 = Access time controlled by TCONCS1.PHE1
669 ; 1 = Access time cont. by TCONCS1.PHE1 and READY signal
670 ;
671 ; <o> RDYMOD1: Ready Mode (FCONCS1.2)
672 ; <0=> Asynchronous <1=> Synchronous
0000 673 _RDYMOD1 EQU 0 ; 0 = Asynchronous READY
674 ; 1 = Synchronous READY
675 ;
676 ; <o> BTYP1: Bus Type Selection (FCONCS1.4 .. FCONCS1.5)
677 ; <0=> 8-bit Demultiplexed Bus <1=> 8-bit Multiplexed Bus
678 ; <2=> 16-bit Demultiplexed Bus <3=> 16-bit Multiplexed Bus
0002 679 _BTYP1 EQU 2 ; 0 = 8 bit Demultiplexed bus
680 ; 1 = 8 bit Multiplexed bus
681 ; 2 = 16 bit Demultiplexed bus
682 ; 3 = 16 bit Multiplexed bus
683 ;</h>
684 ;
685 ; <h>TCONCS1: Definitions for the Timing Configuration register
686 ; =============================================================
687 ;
688 ; <o>PHA1: Phase A clock cycles (TCONCS1.0 .. TCONCS1.1) <0-3>
0000 689 _PHA1 EQU 0 ; 0 = 0 clock cycles
690 ; : = :
691 ; 3 = 3 clock cycles
692 ;
693 ; <o>PHB1: Phase B clock cycles (TCONCS1.2) <1-2> <#-1>
0000 694 _PHB1 EQU 0 ; 0 = 1 clock cycle
695 ; 1 = 2 clock cycles
696 ;
697 ; <o>PHC1: Phase C clock cycles (TCONCS1.3 .. TCONCS1.4) <0-3>
0000 698 _PHC1 EQU 0 ; 0 = 0 clock cycles
699 ; : = :
700 ; 3 = 3 clock cycles
701 ;
702 ; <o>PHD1: Phase D clock cycles (TCONCS1.5) <0-1>
0000 703 _PHD1 EQU 0 ; 0 = 0 clock cycles
704 ; 1 = 1 clock cycle
705 ;
706 ; <o> PHE1: Phase E clock cycles (TCONCS1.6 .. TCONCS1.10) <1-32> <#-1>
0008 707 _PHE1 EQU 8 ; 0 = 1 clock cycle
708 ; : = :
709 ; 31 = 32 clock cycles
710 ;
711 ; <o>RDPHF1: Phase F read clock cycles (TCONCS1.11 .. TCONCS1.12) <0-3>
0000 712 _RDPHF1 EQU 0 ; 0 = 0 clock cycles
713 ; : = :
714 ; 3 = 3 clock cycles
A166 MACRO ASSEMBLER START167 10/01/2008 12:25:59 PAGE 12
715 ;
716 ; <o>WRPHF1: Phase F write clock cycles (TCONCS1.13 .. TCONCS1.14) <0-3>
0003 717 _WRPHF1 EQU 3 ; 0 = 0 clock cycles
718 ; : = :
719 ; 3 = 3 clock cycles
720 ;</h> </e>
721 ;
722 ;<e>Configure External Bus Behaviour for CS2 Area
723 ; =============================================
724 ;
725 ; --- Set CONFIG_CS2 = 1 to initialize the ADDRSEL2/FCONCS2/TCONCS2 registers
726 $SET (CONFIG_CS2 = 1)
727 ;
728 ; <h>Definitions for Address Select register ADDRSEL2
729 ; ===================================================
730 ; <o> CS2 Start Address <0x0-0xFFFFFF:0x1000>
00100000 731 _ADDR2 EQU 0x100000 ; Set CS2# Start Address (default 100000H)
732
733 ; <o> CS2 Size in KB
734 ; <4=> 4KB <8=> 8KB <16=> 16KB <32=> 32KB
735 ; <64=> 64KB <128=> 128KB <256=> 256KB <512=> 512KB
736 ; <1024=> 1024KB <2048=> 2048KB <4096=> 4096KB <8192=> 8192KB
00100000 737 _SIZE2 EQU 1024*KB ; Set CS2# Size (default 1024*KB = 1*MB)
738 ; possible values for _SIZE2 are:
739 ; 4*KB (gives RGSZ2 = 0)
740 ; 8*KB (gives RGSZ2 = 1)
741 ; 16*KB (gives RGSZ2 = 2)
742 ; 32*KB (gives RGSZ2 = 3)
743 ; 64*KB (gives RGSZ2 = 4)
744 ; 128*KB (gives RGSZ2 = 5)
745 ; 256*KB (gives RGSZ2 = 6)
746 ; 512*KB (gives RGSZ2 = 7)
747 ; 1024*KB or 1*MB (gives RGSZ2 = 8)
748 ; 2048*KB or 2*MB (gives RGSZ2 = 9)
749 ; 4096*KB or 4*MB (gives RGSZ2 = 10)
750 ; 8192*KB or 8*MB (gives RGSZ2 = 11)
751 ; (RGSZ2 = 12 .. 15 reserved)
752 ;</h>
753 ;
754 ; <h>Definitions for Function Configuration Register FCONCS2
755 ; ==========================================================
756 ;
757 ; <q> ENCS2: Enable Chip Select (FCONCS2.0)
0001 758 _ENCS2 EQU 1 ; 0 = Chip Select 0 disabled
759 ; 1 = Chip Select 0 enabled
760 ;
761 ; <q> RDYEN2: Ready Enable (FCONCS2.1)
0000 762 _RDYEN2 EQU 0 ; 0 = Access time controlled by TCONCS2.PHE1
763 ; 1 = Access time cont. by TCONCS2.PHE1 and READY signal
764 ;
765 ; <o> RDYMOD2: Ready Mode (FCONCS2.2)
766 ; <0=> Asynchronous <1=> Synchronous
0000 767 _RDYMOD2 EQU 0 ; 0 = Asynchronous READY
768 ; 1 = Synchronous READY
769 ;
770 ; <o> BTYP2: Bus Type Selection (FCONCS2.4 .. FCONCS2.5)
771 ; <0=> 8-bit Demultiplexed Bus <1=> 8-bit Multiplexed Bus
772 ; <2=> 16-bit Demultiplexed Bus <3=> 16-bit Multiplexed Bus
0002 773 _BTYP2 EQU 2 ; 0 = 8 bit Demultiplexed bus
774 ; 1 = 8 bit Multiplexed bus
775 ; 2 = 16 bit Demultiplexed bus
776 ; 3 = 16 bit Multiplexed bus
777 ;</h>
778 ;
779 ; <h>TCONCS2: Definitions for the Timing Configuration register
780 ; =============================================================
A166 MACRO ASSEMBLER START167 10/01/2008 12:25:59 PAGE 13
781 ;
782 ; <o>PHA2: Phase A clock cycle (TCONCS2.0 .. TCONCS2.1) <0-3>
0000 783 _PHA2 EQU 0 ; 0 = 0 clock cycles
784 ; : = :
785 ; 3 = 3 clock cycles
786 ;
787 ; <o>PHB2: Phase B clock cycle (TCONCS2.2) <1-2> <#-1>
0000 788 _PHB2 EQU 0 ; 0 = 1 clock cycle
789 ; 1 = 2 clock cycles
790 ;
791 ; <o>PHC2: Phase C clock cycle (TCONCS2.3 .. TCONCS2.4) <0-3>
0000 792 _PHC2 EQU 0 ; 0 = 0 clock cycles
793 ; : = :
794 ; 3 = 3 clock cycles
795 ;
796 ; <o>PHD2: Phase D clock cycle (TCONCS2.5) <0-1>
0000 797 _PHD2 EQU 0 ; 0 = 0 clock cycles
798 ; 1 = 1 clock cycle
799 ;
800 ; <o> PHE2: Phase E clock cycle (TCONCS2.6 .. TCONCS2.10) <1-32> <#-1>
0008 801 _PHE2 EQU 8 ; 0 = 1 clock cycle
802 ; : = :
803 ; 31 = 32 clock cycles
804 ;
805 ; <o>RDPHF2: Phase F read clock cycle (TCONCS2.11 .. TCONCS2.12) <0-3>
0000 806 _RDPHF2 EQU 0 ; 0 = 0 clock cycles
807 ; : = :
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