📄 start167.lst
字号:
481 ; : = :
482 ; 8 = Eight (A16 .. A23) address pins enabled
483 ; 9 - 15 = reserved
484 ;
485 ; <o> CSPEN: CSx Pins Enabled (EBCMOD0.4 .. EBCMOD0.7) <0-8>
486 ; <i> Number of active ChipSelect pins
0005 487 _CSPEN EQU 5 ; 0 = No CS pins enabled
488 ; 1 = One CS (CS0) pin enabled
489 ; : = :
490 ; 8 = Eight CS (CS0 .. CS7) pins enabled
491 ; 9 - 15 = reserved
492 ; Note: the number of available CS pins depends on the chip used
493 ;
494 ; <q> ARBEN: Enable Bus Arbitration Pins (EBCMOD0.8)
0000 495 _ARBEN EQU 0 ; 0 = HOLD, HLDA and BREQ pins are tristate or act as GPIO
496 ; 1 = HOLD, HLDA and BREQ pins act normally
497 ;
498 ; <o> SLAVE: SLAVE mode enable (EBCMOD0.9)
499 ; <0=> Master Mode <1=> Slave Mode
0000 500 _SLAVE EQU 0 ; 0 = Bus arbiter acts in master mode
501 ; 1 = Bus arbiter acts in slave mode
502 ;
503 ; <q> EBCDIS: Disable EBC pins (EBCMOD0.10)
0000 504 _EBCDIS EQU 0 ; 0 = EBC is using the pins for external bus
505 ; 1 = EBC off (pins to be used as GPIO if implemented)
506 ;
507 ; <o> WRCFG: Configuration for pins WR/WRL and BHE/WRH (EBCMOD0.11)
508 ; <0=> WR and BHE <1=> WRL and WRH
0000 509 _WRCFG EQU 0 ; 0 = Pins act as WR and BHE
510 ; 1 = Pins act as WRL and WRH
511 ;
512 ; <q> BYTDIS: Disable BHE pin (EBCMOD0.12)
0000 513 _BYTDIS EQU 0 ; 0 = BHE enabled
514 ; 1 = BHE disabled (GPIO function if implemented)
515 ;
516 ; <q> ALEDIS: Disable ALE pin (EBCMOD0.13)
A166 MACRO ASSEMBLER START167 10/01/2008 12:25:59 PAGE 9
0001 517 _ALEDIS EQU 1 ; 0 = ALE pin enabled
518 ; 1 = ALE pin disabled (GPIO function if implemented)
519 ;
520 ; <q> RDYDIS: Disable READY pin (EBCMOD0.14)
0000 521 _RDYDIS EQU 0 ; 0 = READY enabled
522 ; 1 = READY disabled (GPIO function if implemented)
523 ;
524 ; <o> RDYPOL: READY pin polarity (EBCMOD0.15)
525 ; <0=> Active Low <1=> Active High
0000 526 _RDYPOL EQU 0 ; 0 = READY pin is active low
527 ; 1 = READY pin is active high
528 ;
529 ;</h>
530 ;
531 ; <h>Definitions for EBC Mode 1 register EBCMOD1
532 ; ==============================================
533 ;
534 ; <o> APDIS: Address Port Pins Disable (EBCMOD1.0 .. EBCMOD1.3) <0-15>
0000 535 _APDIS EQU 0 ; 0 = Address bus pins 15-1 of PORT1 enabled
536 ; 1 = Pin A15 disabled, A14-1 enabled
537 ; 2 = Pin A15-A14 disabled, A13-1 enabled
538 ; ...
539 ; 15 = Pins A15-A1 disabled
540 ;
541 ; <q> A0PDIS: Address Bit 0 Pin Disable (EBCMOD1.4)
0000 542 _A0PDIS EQU 0 ; 0 = Address bus pin 0 of PORT1 enabled
543 ; 1 = Address bus pin 0 of PORT1 disabled
544 ;
545 ; <q> ALPDIS: Address Low Pins Disable (EBCMOD1.5)
0000 546 _ALPDIS EQU 0 ; 0 = Address bus pin 7-0 generally enabled
547 ; 1 = Address bus pin 7-0 of PORT1 disabled
548 ;
549 ; <q> DHPDIS: Data High Port Pins Disable (EBCMOD1.6)
0000 550 _DHPDIS EQU 0 ; 0 = Data bus pins 15-8 of PORT0 enabled
551 ; 1 = Data bus pins 15-8 disabled (used as GPIO)
552 ;
553 ; <q> WRPDIS: WR/WRL Pin Disable (EBCMOD1.7)
0000 554 _WRPDIS EQU 0 ; 0 = WR/WRL pin of Port P20 enabled
555 ; 1 = WR/WRL pin of Port P20 disabled
556 ;
557 ;</h></e>
558 ;
559 ; <e> Configure External Bus Behaviour for CS0 area
560 ; =================================================
561 ;
562 ; --- Set CONFIG_CS0 = 1 to initialize the FCONCS0/TCONCS0 registers
563 $SET (CONFIG_CS0 = 1)
564 ;
565
566 ; <h>Definitions for Function Configuration Register FCONCS0
567 ; ==========================================================
568 ;
569 ; <q> ENCS0: Enable Chip Select (FCONCS0.0)
0001 570 _ENCS0 EQU 1 ; 0 = Chip Select 0 disabled
571 ; 1 = Chip Select 0 enabled
572 ;
573 ; <q> RDYEN0: Ready Enable (FCONCS0.1)
0000 574 _RDYEN0 EQU 0 ; 0 = Access time controlled by TCONCS0.PHE0
575 ; 1 = Access time cont. by TCONCS0.PHE0 and READY signal
576 ;
577 ; <o> RDYMOD0: Ready Mode (FCONCS0.2)
578 ; <0=> Asynchronous <1=> Synchronous
0000 579 _RDYMOD0 EQU 0 ; 0 = Asynchronous READY
580 ; 1 = Synchronous READY
581 ;
582 ; <o> BTYP0: Bus Type Selection (FCONCS0.4 .. FCONCS0.5)
A166 MACRO ASSEMBLER START167 10/01/2008 12:25:59 PAGE 10
583 ; <0=> 8-bit Demultiplexed Bus <1=> 8-bit Multiplexed Bus
584 ; <2=> 16-bit Demultiplexed Bus <3=> 16-bit Multiplexed Bus
0002 585 _BTYP0 EQU 2 ; 0 = 8 bit Demultiplexed bus
586 ; 1 = 8 bit Multiplexed bus
587 ; 2 = 16 bit Demultiplexed bus
588 ; 3 = 16 bit Multiplexed bus
589 ; </h>
590 ;
591 ; <h> TCONCS0: Definitions for the Timing Configuration register
592 ; ==============================================================
593 ;
594 ; <o> PHA0: Phase A clock cycles (TCONCS0.0 .. TCONCS0.1) <0-3>
0000 595 _PHA0 EQU 0 ; 0 = 0 clock cycles
596 ; : = :
597 ; 3 = 3 clock cycles
598 ;
599 ; <o> PHB0: Phase B clock cycles (TCONCS0.2) <1-2> <#-1>
0000 600 _PHB0 EQU 0 ; 0 = 1 clock cycle
601 ; 1 = 2 clock cycles
602 ;
603 ; <o> PHC0: Phase C clock cycles (TCONCS0.3 .. TCONCS0.4) <0-3>
0000 604 _PHC0 EQU 0 ; 0 = 0 clock cycles
605 ; : = :
606 ; 3 = 3 clock cycles
607 ;
608 ; <o> PHD0: Phase D clock cycle (TCONCS0.5) <0-1>
0000 609 _PHD0 EQU 0 ; 0 = 0 clock cycles
610 ; 1 = 1 clock cycle
611 ;
612 ; <o> PHE0: Phase E clock cycles (TCONCS0.6 .. TCONCS0.10) <1-32> <#-1>
0008 613 _PHE0 EQU 8 ; 0 = 1 clock cycle
614 ; : = :
615 ; 31 = 32 clock cycles
616 ;
617 ; <o> RDPHF0: Phase F read clock cycles (TCONCS0.11 .. TCONCS0.12) <0-3>
0000 618 _RDPHF0 EQU 0 ; 0 = 0 clock cycles
619 ; : = :
620 ; 3 = 3 clock cycles
621 ;
622 ; <o> WRPHF0: Phase F write clock cycles (TCONCS0.13 .. TCONCS0.14) <0-3>
0003 623 _WRPHF0 EQU 3 ; 0 = 0 clock cycles
624 ; : = :
625 ; 3 = 3 clock cycles
626 ;</h> </e>
627 ;
628 ; <e> Configure External Bus Behaviour for CS1 Area
629 ; =================================================
630 ;
631 ; --- Set CONFIG_CS1 = 1 to initialize the ADDRSEL1/FCONCS1/TCONCS1 registers
632 $SET (CONFIG_CS1 = 1)
633 ;
634 ; <h>Definitions for Address Select register ADDRSEL1
635 ; ===================================================
636 ; <o> CS1 Start Address <0x0-0xFFFFFF:0x1000>
00010000 637 _ADDR1 EQU 0x010000 ; Set CS1# Start Address (default 100000H)
638
639 ; <o> CS1 Size in KB
640 ; <4=> 4KB <8=> 8KB <16=> 16KB <32=> 32KB
641 ; <64=> 64KB <128=> 128KB <256=> 256KB <512=> 512KB
642 ; <1024=> 1024KB <2048=> 2048KB <4096=> 4096KB <8192=> 8192KB
00010000 643 _SIZE1 EQU 64*KB ; Set CS1# Size (default 1024*KB = 1*MB)
644 ; possible values for _SIZE1 are:
645 ; 4*KB (gives RGSZ1 = 0)
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -