📄 start167.lst
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0000 322 SDLMDIS EQU 0 ; 1 = disable SDLM (J1850) Module (SYSCON3.12)
A166 MACRO ASSEMBLER START167 10/01/2008 12:25:59 PAGE 6
323 ;<q> Disable on-chip CAN Module
0000 324 CANDIS EQU 0 ; 1 = disable on-chip CAN Module (SYSCON3.13)
325 ;<q> Disable Real Time Clock
0000 326 RTCDIS EQU 0 ; 1 = disable Real Time Clock (SYSCON3.14)
327 ;<q> Disable Synchronus Serial Cnl1 SSC1
0000 328 SSC1DIS EQU 0 ; 1 = disable Synchronus Serial Cnl1 SSC1 (SYSCON3.15)
329 ;
330 ;</e>
331 ;</h>
332 ; <e> Definitions for Reset Configuration Register RSTCON
333 ; =======================================================
334 ;
335 ; INIT_RSTCON: Init RSTCON register
336 ; --- Set INIT_RSTCON = 1 to initialize the RSTCON register
337 $SET (INIT_RSTCON = 1)
338 ;
339 ; <o> RSTLEN: Reset Length Control (RSTCON.0 .. RSTCON.2)
340 ; <0=> 2 CPU clocks <1=> 4 CPU clocks <2=> 8 CPU clocks <3=> 16 CPU clocks
341 ; <4=> 32 CPU clocks <5=> 64 CPU clocks <6=> 128 CPU clocks <7=> 256 CPU clocks
0000 342 _RSTLEN EQU 0 ; 0 = 2 t_CPU clocks (default)
343 ; 1 = 4 t_CPU clocks
344 ; 2 = 8 t_CPU clocks
345 ; 3 = 16 t_CPU clocks
346 ; 4 = 32 t_CPU clocks
347 ; 5 = 64 t_CPU clocks
348 ; 6 = 128 t_CPU clocks
349 ; 7 = 256 t_CPU clocks
350 ;
351 ; <o> RORMV: RSTOUT# Remove Control (RSTCON.4)
352 ; <0=> RSTOUT delivers RSTOUT# signal <1=> RSTOUT pin operates as GPIO
0000 353 _RORMV EQU 0 ; 0 = RSTOUT delivers RSTOUT# signal
354 ; 1 = RSTOUT pin operates as GPIO
355 ;
356 ; <o> ROCOFF: RSTOUT# Control Switch Off (RSTCON.5)
357 ; <0=>RSTOUT deactivated by user software <1=>RSTOUT deactivated after reset
0000 358 _ROCOFF EQU 0 ; 0 = RSTOUT is deactivated by user software
359 ; 1 = RSTOUT is deactivated at end of reset
360 ;
361 ; <o> ROCON: RSTOUT# Control Switch Off (RSTCON.6)
362 ; <0=> RSTOUT active on any reset <1=> RSTOUT active on hardware reset
0000 363 _ROCON EQU 0 ; 0 = RSTOUT is activated upon any reset
364 ; 1 = RSTOUT is only activated upon a hardware reset
365 ;
366 ; <q> RODIS: RSTOUT# Disable Control (RSTCON.7) <0-1>
0000 367 _RODIS EQU 0 ; 0 = RSTOUT is controlled by other mechanism
368 ; 1 = RSTOUT is deactivated
369 ;
370 ;</e>
371 ;
372 ;
373 ; <e> Definitions for PLL Control Register PLLCON
374 ; ===============================================
375 ;
376 ; INIT_PLLCON: Init PLLCON register
377 ; --- Set INIT_PLLCON = 1 to initialize the PLLCON register
378 $SET (INIT_PLLCON = 1)
379 ;
380 ; <o> PLLODIV: PLL Output Divider (PLLCON.0 .. PLLCON.3) <0-14>
0004 381 _PLLODIV EQU 4 ; 0 .. 14 Fpll = Fvco / (PLLODIV+1)
382 ; 15 = reserved
383 ;
384 ; <o> PLLIDIV: PLL Input Divider (PLLCON.4 .. PLLCON.5) <0-3>
385 ; <i> Fin = Fosc / (PLLIDIV+1)
0001 386 _PLLIDIV EQU 1 ; 0 .. 3 Fin = Fosc / (PLLIDIV+1)
387 ;
388 ; <o> PLLVB: PLL VCO Band Select (PLLCON.6 .. PLLCON.7)
A166 MACRO ASSEMBLER START167 10/01/2008 12:25:59 PAGE 7
389 ; <0=> Ouput:100-150MHz / Base:20-80MHz <1=> Ouput:150-200MHz / Base:40-130MHz
390 ; <2=> Ouput:200-250MHz / Base:60-180MHz <3=> (250...300 MHz) Reserved
0002 391 _PLLVB EQU 2 ; ValueVCO output frequency Base frequency
392 ; 0 = 100...150 MHz 20...80 MHz
393 ; 1 = 150...200 MHz 40...130 MHz
394 ; 2 = 200...250 MHz [def.] 60...180 MHz
395 ; 3 = (250...300 MHz) Reserved
396 ;
397 ; <o> PLLMUL: PLL Multiplication Factor (PLLCON.8 .. PLLCON.12) <6-31>
398 ; <i> Fvco = Fin * (PLLMUL+1)
0018 399 _PLLMUL EQU 24 ; 7 .. 31 Fvco = Fin * (PLLMUL+1)
400 ; 0 .. 6 = reserved
401 ;
402 ; <o> PLLCTRL: PLL Operation Control (PLLCON.13 .. PLLCON.14)
403 ; <0=> Bypass PLL clock mult., the VCO is off <1=> Bypass PLL clock mult., the VCO i
s running
404 ; <2=> VCO clock used, input clock switched off <3=> VCO clock used, input clock conne
cted
0003 405 _PLLCTRL EQU 3 ; 0 = Bypass PLL clock mult., the VCO is off
406 ; 1 = Bypass PLL clock mult., the VCO is running
407 ; 2 = VCO clock used, input clock switched off
408 ; 3 = VCO clock used, input clock connected
409 ;
410 ; <o> PLLWRI: PLLCON Write Ignore Flag (PLLCON.15)
411 ; <0=> Register PLLCON may be written <1=> Write cycles to register PLLCON are ignore
d
0000 412 _PLLWRI EQU 0 ; 0 = Register PLLCON may be written
413 ; 1 = Write cycles to register PLLCON are ignored
414 ;</e>
415 ;
416 ; <e> Definitions for Watchdog Timer Control Register WDTCON
417 ; ==========================================================
418 ;
419 ; --- Set WATCHDOG = 0 to enable the Hardware watchdog and initialize the WDTCON regis
ter
420 $SET (WATCHDOG = 0) ; 0 = Disabled Hardware watchdog
421 ;
422 ; <o> WDTIN: Watchdog Timer Input Frequency Select (WDTCON.0 .. WDTCON.1)
423 ; <0=> Peripheral Frequency divided by 2 <1=> Peripheral Frequency divided by 128
424 ; <2=> Peripheral Frequency divided by 4 <3=> Peripheral Frequency divided by 256
0001 425 _WDTIN EQU 1 ; 0 = frequency f_peripheral / 2 (CPU default)
426 ; 1 = frequency f_peripheral / 128 (recommended for START_V2)
427 ; 2 = frequency f_peripheral / 4
428 ; 3 = frequency f_peripheral / 256
429 ;
430 ; <o> WDTREL: Watchdog Timer Reload Value (WDTCON8 .. WDTCON15) <0-255>
431 ; <i> High byte of WDT (counts up, overflow gives Watchdog reset)
0000 432 _WDTREL EQU 0
433 ;
434 ;</e>
435 ; <e> Definitions for Frequency Output Signal FOCON
436 ; =================================================
437 ;
438 ; INIT_FOCON: Init FOCON register
439 ; --- Set INIT_FOCON = 0 to initialize the FOCON register
440 $SET (INIT_FOCON = 1)
441 ;
442 ; <o> CLKEN: CLKOUT Enable (FOCON.7)
443 ; <0=> P3.15 is IO <1=> P3.15 is CLKOUT
0000 444 _CLKEN EQU 0 ; 0 = P3.15 is IO pin when _FOUT is 0
445 ; 1 = P3.15 outputs signal CLKOUT
446 ;
447 ; <o> FORV: Frequency Output Reload Value (FOCON.8 .. FOCON.13) <0-63>
448 ; <i> Is copied to FOCNT upon each underflow of FOCNT
0000 449 _FORV EQU 0
450 ;
A166 MACRO ASSEMBLER START167 10/01/2008 12:25:59 PAGE 8
451 ; <o> FOSS: Frequency Output Signal Select (FOCON.14)
452 ; <0=> Output of Toggle Latch <1=> Output of Reload Counter
0000 453 _FOSS EQU 0 ; 0 = Output of the toggle latch; 0.5 duty cycle
454 ; 1 = Output of reload counter; duty cycle depends on FORV
455 ;
456 ; <o> FOEN: Frequency Output Enable (FOCON.15)
457 ; <0=> P3.15 is IO <1=> P3.15 outputs f_OUT
0000 458 _FOEN EQU 0 ; 0 = P3.15 is IO pin when _CLKEN is 0
459 ; 1 = P3.15 outputs f_OUT when _CLKEN is 0
460 ;</e>
461 ;
462 ;<h> External Bus Configuration
463 ;
464 ; <e> Configure External Bus (EBC) Behaviour
465 ; ==========================================
466 ;
467 ; --- Set CONFIG_EBC = 0 to initialize the EBCMOD0/EBCMOD1 registers
468 $SET (CONFIG_EBC = 1) ; 0 = EBCMOD0/EBCMOD1 are set during reset according the
469 ; of configuration bus (typical Port0) values.
470 ; 1 = the following external bus configuration values
471 ; are written to EBCMOD and BUSACT0
472 ;
473 ; <h> Definitions for EBC Mode 0 register EBCMOD0
474 ; ===============================================
475 ;
476
477 ; <o> SAPEN: Segment Address Pins Enabled (EBCMOD0.0 .. EBCMOD0.3) <0-8>
478 ; <i> Number of active Address Lines (A16-A23)
0005 479 _SAPEN EQU 5 ; 0 = No segment address pins enabled
480 ; 1 = One (A16) segment address pin enabled
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