📄 start167.lst
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0001 157 _RETST EQU 1 ; 0 = Return Stack disabled
158 ; 1 = Return Stack enabled
159 ;
160 ; <q> OVRUN: Pipeline Control (CPUCON2.4)
0001 161 _OVRUN EQU 1 ; 0 = Overrun of Pipeline Bubbles not allowed
162 ; 1 = Overrun of Pipeline Bubbles allowed
163 ;
164 ; <q> LFIC: Linear Follower Instruction Cache (CPUCON2.5)
0001 165 _LFIC EQU 1 ; 0 = Linear Follower Instruction Cache disabled
166 ; 1 = Linear Follower Instruction Cache enabled
167 ;
168 ; <q> STEN: Stall Instruction Enable (CPUCON2.6)
0000 169 _STEN EQU 0 ; 0 = Stall instruction disabled
170 ; 1 = Stall instruction enabled
171 ;
172 ; <q> EIOIAEN: Early IO Injection Acknowledge Enable (CPUCON2.7)
0001 173 _EIOIAEN EQU 1 ; 0 = Injection ack. by destructive read not guaranteed
174 ; ; 1 = Injection ack. by destructive read guaranteed
175 ;
176 ; <q> BYPF: Fetch Bypass Control (CPUCON2.8)
0001 177 _BYPF EQU 1 ; 0 = Bypass Path from Fetch to Decode disabled
178 ; 1 = Bypass Path from Fetch to Decode enabled
179 ;
180 ; <q> BYPPF: Enable Prefecth Bypass Control (CPUCON2.9)
0001 181 _BYPPF EQU 1 ; 0 = Bypass Path from Prefetch to Decode disabled
182 ; 1 = Bypass Path from Prefetch to Decode enabled
183 ;
184 ; <o> FIFOFED: FIFO Fed Configuration (CPUCON2.10 .. CPUCON2.11)
185 ; <0=> FIFO disabled <1=> 1 instruction
186 ; <2=> 2 instructions <3=> 3 instructions
0003 187 _FIFOFED EQU 3 ; 0 = FIFO disabled
188 ; 1 = FIFO filled with up to 1 instruction per cycle
189 ; 2 = FIFO filled with up to 2 instructions per cycle
190 ; 3 = FIFO filled with up to 3 instructions per cycle
A166 MACRO ASSEMBLER START167 10/01/2008 12:25:59 PAGE 4
191 ;
192 ;<o> FIFODEPTH: FIFO Depth Configuration (CPUCON2.12 .. CPUCON2.15) <0-8>
0008 193 _FIFODEPTH EQU 8 ; 0 = No FIFO entries (No FIFO)
194 ; 1 = 1 FIFO entry
195 ; ...
196 ; 8 = 8 FIFO entries
197 ; 9 - 15 = reserved
198 ;</e>
199
200 ; <e> Definitions for Internal Memory Block Control Register IMBCTR
201 ; =================================================================
202 ;
203 ; INIT_IMBCTR: Init IMBCTR register
204 ; --- <i>Set INIT_IMBCTR = 1 to initialize the IMBCTR register
205 $SET (INIT_IMBCTR = 0) ; default: do not initialize IMBCTR
206 ;
207 ; <o> WSFLASH: Wait States for the Flash Memory (IMBCTR.0 .. IMBCTR.1)
208 ; <0=> No waitstates (Flash Read in one clock)
209 ; <1=> One waitstate (Flash Read in two clocks)
210 ; <2=> Two waitstates (Flash Read in three clocks)
211 ; <3=> Three waitstates (Flash Read in four clocks)
0001 212 _WSFLASH EQU 1 ; 0 = No waitstates
213 ; 1 = One waitstate
214 ; 2 = Two waitstates
215 ; 3 = Three waitstates
216 ;
217 ; <q> WSRAM: Wait State for Program RAM Access (IMBCTR.2)
218 ; <i> when enabled, Program SRAM has same timing behaviour as Flash memory
0000 219 _WSRAM EQU 0 ; 0 = Program SRAM accessed with max. speed
220 ; 1 = Program SRAM access like Flash Memory
221 ;
222 ;</e>
223
224 ;</h>
225 ; <e> OCDS Debug Peripheral Suspend Configuration
226 ; ===============================================
227 ; <i> Initialize OPSEN to stop specific peripherals during debugging
0000 228 _OCDS_PSTOP EQU 0 ; 0 = OPSEN is not modified by startup code
229 ; 1 = OPSEN is modified with the value below
230 ; <i> Selects the peripherals that are halted by OCDS debugging
231 ; <i> when a breakpoint is reached
232 ; <q.0> Stop Analog/Digital Converter
233 ; <q.1> Stop UART ASC0
234 ; <q.2> Stop Synchronus Serial Cnl0 SSC0
235 ; <q.3> Stop Timer Block GPT
236 ; bit 4 reserved
237 ; <q.5> Stop on-chip Flash Memory Module
238 ; <q.6> Stop CAPCOM Unit 1
239 ; <q.7> Stop CAPCOM Unit 2
240 ; <q.8> Stop CAPCOM Unit 6
241 ; bit 9 reserved
242 ; <q.10> Stop UART ASC1
243 ; <q.11> Stop I2C Bus Module
244 ; <q.12> Stop SDLM (J1850) Module
245 ; <q.13> Stop on-chip CAN Module
246 ; <q.14> Stop Real Time Clock
247 ; <q.15> Stop Synchronus Serial Cnl1 SSC1
248
249 ; value for OPSEN (OCE/OCDS Peripheral Suspend Register)
0000 250 _OPSEN EQU 0
251 ;</e>
252
253 ; <h> Peripheral Configuration
254 ; ============================
255 ;
256 ; <e> Definitions for System Configuration Register SYSCON1
A166 MACRO ASSEMBLER START167 10/01/2008 12:25:59 PAGE 5
257 ; =========================================================
258 ;
259 ; INIT_SYSCON1: Init SYSCON1 register
260 ; --- Set INIT_SYSCON1 = 1 to initialize the SYSCON1 register
261 $SET (INIT_SYSCON1 = 0)
262 ;
263 ; <q> SLEEPCON: Sleep Mode Configuration (SYSCON1.0 .. SYSCON1.1)
264 ; <0=> IDLE mode upon IDLE instr. <1=> SLEEP mode upon IDLE instr.
0000 265 _SLEEPCON EQU 0 ; 0 = Normal IDLE mode entered upone IDLE instruction
266 ; 1 = SLEEP mode entered upon IDLE instruction
267 ; 2 - 3 = reserved
268 ;
269 ; <q> PDCFG: Port Driver Configuration (SYSCON1.2 .. SYSCON1.3)
270 ; <0=>Port drivers are always ON <1=>Port drivers are off in IDLE/Sleep mode
271 ; <2=>Port drivers are off in Powerdown mode
0000 272 _PDCFG EQU 0 ; 0 = Port drivers are always ON (default)
273 ; 1 = Port drivers are off in IDLE or Sleep mode
274 ; 2 = Port drivers are off in Powerdown mode
275 ; 3 = reserved
276 ;
277 ; <o> PFCFG: Program Flash Configuration (SYSCON1.4 .. SYSCON1.5)
278 ; <0=> Program Flash always ON <1=>Program Flash OFF in IDLE/Sleep mode
0000 279 _PFCFG EQU 0 ; 0 = Program Flash is always ON (default)
280 ; 1 = Program Flash is off in IDLE or Sleep mode
281 ; 2 - 3 = reserved
282 ;
283 ; <o> CPSYS: Clock Prescaler for System (SYSCON1.8 .. SYSCON1.10)
284 ; <0=>CPU clock = PLL frequency <1=>CPU clock = PLL frequency / 2
0000 285 _CPSYS EQU 0 ; 0 = clock signal for CPU is PLL frequency
286 ; 1 = clock signal for CPU is PLL frequency / 2
287 ; 2 - 7 = reserved
288 ; </e>
289 ;
290 ; <e> Definitions for System Configuration Register SYSCON3
291 ; =========================================================
292 ;
293 ; INIT_SYSCON3: Init SYSCON3 register
294 ; --- Set INIT_SYSCON3 = 1 to initialize the SYSCON3 register
295 $SET (INIT_SYSCON3 = 1)
296 ;
297 ; SYSCON3: Power Management (disable on-chip peripherals)
298 ;
299 ;<q> Disable Analog/Digital Converter
0000 300 ADCDIS EQU 0 ; 1 = disable Analog/Digital Converter (SYSCON3.0)
301 ;<q> Disable UART ASC0
0000 302 ASC0DIS EQU 0 ; 1 = disable UART ASC0 (SYSCON3.1)
303 ;<q> Disable Synchronus Serial Cnl0 SSC0
0000 304 SSC0DIS EQU 0 ; 1 = disable Synchronus Serial Cnl0 SSC0 (SYSCON3.2)
305 ;<q> Disable Timer Block GPT
0000 306 GPTDIS EQU 0 ; 1 = disable Timer Block GPT (SYSCON3.3)
307 ; reserved (SYSCON3.4)
308 ;<q> Disable on-chip Flash Memory Module
0000 309 FMDIS EQU 0 ; 1 = disable on-chip Flash Memory Module (SYSCON3.5)
310 ;<q> Disable CAPCOM Unit 1
0000 311 CC1DIS EQU 0 ; 1 = disable CAPCOM Unit 1 (SYSCON3.6)
312 ;<q> Disable CAPCOM Unit 2
0000 313 CC2DIS EQU 0 ; 1 = disable CAPCOM Unit 2 (SYSCON3.7)
314 ;<q> Disable CAPCOM Unit 6
0000 315 CC6DIS EQU 0 ; 1 = disable CAPCOM Unit 6 (SYSCON3.8)
316 ; reserved (SYSCON3.9)
317 ;<q> Disable UART ASC1
0000 318 ASC1DIS EQU 0 ; 1 = disable UART ASC1 (SYSCON3.10)
319 ;<q> Disable I2C Bus Module
0000 320 I2CDIS EQU 0 ; 1 = disable I2C Bus Module (SYSCON3.11)
321 ;<q> Disable SDLM (J1850) Module
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